公开(公告)号：US20190006415A1

公开(公告)日：2019-01-03

申请号：US15639099

申请日：2017-06-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jimmy Jianan Kan ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path is disclosed. The MRAM includes an MRAM array that includes MRAM bit cell rows each including a plurality of MRAM bit cells. MRAM bit cells on an MRAM bit cell row share a common electrode to provide a shared write operation circuit path for write operations. Dedicated read operation circuit paths are also provided for each MRAM bit cell separate from the write operation circuit path. As a result, the read operation circuit paths for the MRAM bit cells do not vary as a result of the different layout locations of the MRAM bit cells with respect to the common electrode. Thus, the read parasitic resistances of the MRAM bit cells do not vary from each other because of their different coupling locations to the common electrode.

公开(公告)号：US10170610B1

公开(公告)日：2019-01-01

申请号：US15922951

申请日：2018-03-16

Applicant: QUALCOMM Incorporated

Inventor： Gengming Tao ,  Bin Yang ,  Xia Li

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/66

Abstract: In certain aspects, a pseudomorphic high electron mobility transistor (pHEMT) comprises a substrate layer, a bottom barrier layer on the substrate layer, a channel layer on the bottom barrier layer, an upper barrier on the channel layer, and a source and a drain on the upper barrier layer. The source and the drain each has a cap layer, an Ohmic contact layer on the cap layer, and a metal contact layer on the Ohmic contact layer. The Ohmic contact layer has a smaller bandgap than the cap layer. The pHEMT further comprises a gate metal stack on the upper barrier layer.

公开(公告)号：US10102898B2

公开(公告)日：2018-10-16

申请号：US15829004

申请日：2017-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Seung Hyuk Kang

IPC: G11C11/22 ,  G11C13/00 ,  H01L21/02 ,  H01L27/1159 ,  H01L29/49 ,  H01L29/47 ,  H01L29/51 ,  H01L29/16 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/786

Abstract: Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.

公开(公告)号：US10062683B1

公开(公告)日：2018-08-28

申请号：US15587837

申请日：2017-05-05

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

IPC: H01L29/15 ,  H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H01L29/737 ,  H01L29/20 ,  H01L23/532 ,  H01L23/535 ,  H01L21/8252 ,  H01L21/768 ,  H01L23/66

Abstract: An integrated compound semiconductor circuit including a high-Q passive device may include a compound semiconductor transistor. The integrated compound semiconductor circuitry may also include a high-Q inductor device. The integrated compound semiconductor may further include a back-end-of-line interconnect layer electrically contacting the high-Q inductor device and the compound semiconductor transistor, the back-end-of-line interconnect layer comprising a gold base layer and a copper interconnect layer.

公开(公告)号：US10043967B2

公开(公告)日：2018-08-07

申请号：US14454509

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan Chen ,  Xiaochun Zhu ,  Xia Li ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

公开(公告)号：US09997617B2

公开(公告)日：2018-06-12

申请号：US13799955

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/765 ,  H01L27/02 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/7624 ,  H01L21/765 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/785

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

公开(公告)号：US20180102472A1

公开(公告)日：2018-04-12

申请号：US15819993

申请日：2017-11-21

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12 ,  H01L23/544 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

公开(公告)号：US09799824B2

公开(公告)日：2017-10-24

申请号：US15170851

申请日：2016-06-01

Applicant: QUALCOMM Incorporated

Inventor： William H. Xia ,  Wenqing Wu ,  Kendrick H. Yuen ,  Abhishek Banerjee ,  Xia Li ,  Seung H. Kang ,  Jung Pill Kim

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/08 ,  H01L43/12

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

公开(公告)号：US09647037B2

公开(公告)日：2017-05-09

申请号：US14835314

申请日：2015-08-25

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1683

Abstract: A method of fabrication of a device includes forming a first electrode and a second electrode. The method further includes forming a resistive material between the first electrode and the second electrode to form a resistance-based storage element of a resistive random access memory (RRAM) device.

公开(公告)号：US09620612B2

公开(公告)日：2017-04-11

申请号：US14625974

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Xia Li

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L27/08 ,  H01L27/088 ,  H01L21/28 ,  H01L27/11592 ,  G11C11/22

CPC classification number: H01L29/66833 ,  G11C11/221 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/324 ,  H01L27/088 ,  H01L27/11568 ,  H01L27/11592 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78 ,  H01L29/785

Abstract: An integrated circuit device includes a first transistor structure formed in a memory region (e.g., an embedded memory region) of a die. The first transistor structure includes a substrate (e.g., a planar substrate of a planar FET or a fin of a FinFET) and a first gate. The first gate includes a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer. The integrated circuit device further includes a second transistor structure formed in a logic device region of the die. The second transistor structure includes a second gate that includes an interface layer, a dielectric layer, and a cap layer. The dielectric layer is formed between the cap layer and the interface layer.