公开(公告)号：US09313058B2

公开(公告)日：2016-04-12

申请号：US14459132

申请日：2014-08-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee

IPC: H04B1/00 ,  H04L25/40 ,  H04L7/04 ,  H03L7/00 ,  H04L7/027 ,  H04L7/033 ,  H04L25/493

CPC classification number: H04L25/40 ,  H03L7/00 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14 ,  H04L25/493

Abstract: A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

Abstract translation: 多个线路接口被配置为在多个线路接口上接收扩展信号。 扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。 扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。 基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。 基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。 时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的 通过不同线路接口接收的信号。

公开(公告)号：US20150365226A1

公开(公告)日：2015-12-17

申请号：US14834219

申请日：2015-08-24

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/027 ,  H04L25/14

CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

公开(公告)号：US20150319013A1

公开(公告)日：2015-11-05

申请号：US14796207

申请日：2015-07-10

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley

IPC: H04L25/02 ,  H04L25/49 ,  H04L27/22

CPC classification number: H04L25/4917 ,  H04L5/20 ,  H04L7/033 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L27/22

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract translation: 提供了高速串行接口。 一方面，高速串行接口使用三相调制来共同编码数据和时钟信息。 因此，消除了在接口的接收端处对偏斜电路的需要，从而减少了链路启动时间，并提高了链路效率和功耗。 在一个实施例中，高速串行接口使用比具有用于数据和时钟信息的单独导体的传统系统更少的信号导体。 在另一个实施例中，串行接口允许以任何速度发送数据，而没有接收端具有传输数据速率的先前知识。 另一方面，高速串行接口使用极性编码的三相调制来共同编码数据和时钟信息。 这进一步增加了串行接口的链路容量，允许在任何单个波特率间隔内传输多于一个位。

公开(公告)号：US09172426B2

公开(公告)日：2015-10-27

申请号：US14199064

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley ,  Shoichiro Sengoku

IPC: H04B3/00 ,  H04L25/00 ,  H04B3/06 ,  G06F13/40

CPC classification number: H04B3/06 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。 数据被映射到要在多根线上传输的符号序列。 符号序列被编码为三个信号。 可以驱动三个端子中的每一个，使得晶体管被激活以在端子否则将不被引导时通过一对阻抗将端子耦合到第一和第二电压电平。 然后将终端拉向中间电压电平，同时终端向传输线呈现期望的阻抗电平。

公开(公告)号：US20140348214A1

公开(公告)日：2014-11-27

申请号：US14459132

申请日：2014-08-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee

IPC: H04B1/7073

CPC classification number: H04L25/40 ,  H03L7/00 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14 ,  H04L25/493

Abstract: A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

Abstract translation: 多个线路接口被配置为在多个线路接口上接收扩展信号。 扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。 扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。 基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。 基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。 时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的 通过不同线路接口接收的信号。

公开(公告)号：US20140286466A1

公开(公告)日：2014-09-25

申请号：US14220056

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

IPC: H04L7/04

CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

公开(公告)号：US20140270005A1

公开(公告)日：2014-09-18

申请号：US14210246

申请日：2014-03-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L27/20

CPC classification number: H04L27/2071 ,  G06F13/4063 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/0272 ,  H04L25/0292 ,  H04L69/18

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。

公开(公告)号：US20140254732A1

公开(公告)日：2014-09-11

申请号：US14199898

申请日：2014-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入到原始符号的传输中，因为从转换数转换为顺序符号，从而确保没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。

公开(公告)号：US20130241759A1

公开(公告)日：2013-09-19

申请号：US13797272

申请日：2013-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： George Alan Wiley ,  Glenn D. Raskin

IPC: G08C19/16

CPC classification number: G08C19/16 ,  H04L25/0272

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 选择性地将数据作为N相极性编码的符号或作为差分驱动的连接器上的分组发送。 数据传输方法包括以多个连接器传输的符号序列中的数据和控制信号进行编码，以及在多个连接器上发送符号序列。 可以使用第一对连接器的相位状态，第二对连接器的极性和至少一个未驱动连接器的选择的组合来发送每个符号。 符号序列中的每个符号的传输可能导致多个连接器中的至少一个连接器的状态改变。

公开(公告)号：US11720512B2

公开(公告)日：2023-08-08

申请号：US17363407

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Maxime Leclercq ,  George Alan Wiley

IPC: G06F13/40 ,  G06F13/38 ,  H04L43/0817

CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4068 ,  H04L43/0817

Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.