公开(公告)号：US09430027B2

公开(公告)日：2016-08-30

申请号：US14799362

申请日：2015-07-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F1/32 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/04

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20160125930A1

公开(公告)日：2016-05-05

申请号：US14931513

申请日：2015-11-03

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US09170894B2

公开(公告)日：2015-10-27

申请号：US14200665

申请日：2014-03-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract translation: 提供了用于检测和校正存储器系统中的地址错误的系统和方法。 在存储器系统中，存储器件基于通过地址总线发送的地址生成错误检测码，并将错误检测码发送到存储器控制器。 存储器控制器响应于错误检测码向存储器件发送错误指示。 错误指示使存储器件移除接收的地址并防止存储器操作。

公开(公告)号：US20150206562A1

公开(公告)日：2015-07-23

申请号：US14672442

申请日：2015-03-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/00 ,  G06F13/4273 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1075 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

Abstract translation: 存储器模块包括具有用于将数据作为相应数据组传送的模块数据组端口的模块接口，用于接收存储器访问命令的命令端口，包括第一设备数据组端口的第一存储设备，包括第 第二设备数据组端口和耦合在模块接口与第一和第二设备中的每一个之间的信号缓冲器。 在第一模式中，响应于存储器访问命令，信号缓冲器经由模块数据组端口中的相应一个与第一和第二设备数据组端口中的每一个相关联地传送数据组。 在第二模式中，响应于存储器访问命令，信号缓冲器交替地通过与第二设备数据组端口相关联的数据组或与第二设备数据组端口相关联的数据组通过相同的一个 模块数据组端口。

公开(公告)号：US20150170724A1

公开(公告)日：2015-06-18

申请号：US14613270

申请日：2015-02-03

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

Abstract translation: 系统具有以飞越拓扑布置的多个存储器件，每个存储器件具有用于连接到地址和控制（RQ）总线的片上终端（ODT）电路。 每个存储器件的ODT电路包括一组一个或多个控制寄存器，用于控制RQ总线的一个或多个信号线的管芯端接。 第一存储器件包括存储第一ODT值的一个或多个控制寄存器的第一组，用于控制由第一存储器件的ODT电路终止RQ总线的一个或多个信号线，第二存储器器件包括： 存储与第一ODT值不同的第二ODT值的一个或多个控制寄存器的第二组，用于控制由第二存储器件的ODT电路终止RQ总线的一个或多个信号线。

公开(公告)号：US20140112084A1

公开(公告)日：2014-04-24

申请号：US14088277

申请日：2013-11-22

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C11/4063

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.

Abstract translation: 公开了一种存储器控制器。 存储器控制器被配置为经由地址和控制（RQ）总线连接到一个或多个存储器件。 每个存储器件具有连接到RQ总线的信号线子集的片上终端（ODT）电路，并且存储器控制器可操作地选择性地禁用该一个或多个存储器的至少一个存储器件中的ODT电路 设备。

公开(公告)号：US08555116B1

公开(公告)日：2013-10-08

申请号：US13666918

申请日：2012-11-01

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

公开(公告)号：US20130258755A1

公开(公告)日：2013-10-03

申请号：US13845503

申请日：2013-03-18

Applicant: RAMBUS, INC.

Inventor： Ravindranath Kollipara ,  Lei Luo ,  Ian Shaeffer

IPC: G11C11/401

CPC classification number: G11C11/401 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084

Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.

Abstract translation: 实施例涉及具有可编程输入电容的集成电路器件。 例如，存储器件的可编程寄存器可以存储代表控制引脚的输入电容值的调整值。 一个实施例旨在通过允许较轻负载的引脚的可编程性来控制同步存储器系统的偏斜，以便增加它们的负载以匹配负载较重的引脚。 通过将较轻负载的引脚匹配到负载较重的引脚，系统表现出改进的控制和地址引脚的传播延迟同步。 此外，实施例提供了根据设备上多少等级来改变负载的能力。

公开(公告)号：US20250103531A1

公开(公告)日：2025-03-27

申请号：US18919179

申请日：2024-10-17

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US20240330207A1

公开(公告)日：2024-10-03

申请号：US18590200

申请日：2024-02-28

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/1458 ,  G06F3/0619 ,  G06F12/023 ,  G06F13/16 ,  G06F13/1657 ,  G06F13/1684 ,  G06F13/1694 ,  G06F2212/1044 ,  G06F2212/1052

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.