公开(公告)号：US06380084B1

公开(公告)日：2002-04-30

申请号：US09678621

申请日：2000-10-02

申请人： Yeow Kheng Lim ,  Alex See ,  Cher Liang Cha ,  Subhash Gupta ,  Wang Ling Goh ,  Man Siu Tse

发明人： Yeow Kheng Lim ,  Alex See ,  Cher Liang Cha ,  Subhash Gupta ,  Wang Ling Goh ,  Man Siu Tse

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.

摘要翻译： 已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。 沉积在氮化硅层上的第一介电层。 屏蔽层被沉积。 将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。 沉积第一势垒层以对沟槽进行排列。 通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。 第一个铜层被抛光以完成通孔。 沉积第二阻挡层。 图案化第二阻挡层以形成通孔。 沉积第二介电层。 沉积覆盖层。 图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。 沉积第三阻挡层以对连接线沟槽进行排列。 蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。 连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。 第二个铜层被抛光。

公开(公告)号：US06365508B1

公开(公告)日：2002-04-02

申请号：US09618264

申请日：2000-07-18

申请人： Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi ,  Simon Chooi ,  Yakub Aliyu

发明人： Mei Sheng Zhou ,  John Sudijono ,  Subhash Gupta ,  Sudipto Roy ,  Paul Ho ,  Xu Yi ,  Simon Chooi ,  Yakub Aliyu

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76826

摘要： A new method to avoid post-etch cleaning in a metallization process is described. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts is as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.

摘要翻译： 描述了在金属化过程中避免蚀刻后清洁的新方法。 在覆盖半导体衬底的电介质层中的第一金属线上形成绝缘层。 通孔开口通过绝缘层蚀刻到第一金属线，由此在通孔开口的侧壁上形成聚合物。 用氟化剂处理聚合物，由此将聚合物转化为惰性层。 此后，在通孔开口内形成第二金属线，其中惰性层作为阻挡层，以在集成电路器件的制造中完成金属化工艺。

公开(公告)号：US06358821B1

公开(公告)日：2002-03-19

申请号：US09619376

申请日：2000-07-19

申请人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

发明人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

IPC分类号： H01L2122

CPC分类号： H01L21/3221 ,  C23C14/165 ,  H01L21/2885

摘要： A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.

摘要翻译： 一种防止半导体晶片上的铜传输的方法，包括以下步骤。 提供具有正面和背面的半导体晶片。 从包括铝，铝 - 铜，铝 - 硅和铝 - 铜 - 硅的组中选择的金属溅射在晶片的背面以形成一层金属。 背面溅射的铝层可以在低温下部分氧化，以进一步降低铜的渗透可能性，并且在随后的铜互连相关处理中也提供更大的灵活性。 一旦背面层就位，就可以照常处理晶片。 最后的背面研磨可以除去溅射的背面铝层。

公开(公告)号：US06352917B1

公开(公告)日：2002-03-05

申请号：US09598691

申请日：2000-06-21

申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L21/76885 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects. The patterning comprises partially etching down the damascene interconnects using a via mask overlying and protecting portions of the damascene interconnects. A trench mask also overlies and protects the first dielectric layer from metal contamination during the etching down.

摘要翻译： 已经实现了在集成电路器件的制造中形成包含镶嵌互连和通孔插塞的金属互连级别的新方法。 该方法创建一个反向的双镶嵌结构。 第一电介质层设置在半导体衬底上。 图案化电介质层以形成用于计划的大马士革互连的沟槽。 可以可选地在沟槽侧壁上形成绝缘间隔物。 导电阻挡层沉积在电介质层上并衬在沟槽上。 沉积优选包含铜的金属层，覆盖在导电阻挡层上并填充沟槽。 金属层和导电阻挡层被抛光，从而形成镶嵌互连。 可以任选地沉积钝化层。 大马士革互连被图案化以形成覆盖大马士革互连的通孔塞。 图案化包括使用覆盖并保护大马士革互连部分的通孔掩模部分地蚀刻镶嵌互连。 在蚀刻过程中，沟槽掩模也覆盖并保护第一介电层免受金属污染。

公开(公告)号：US06348407B1

公开(公告)日：2002-02-19

申请号：US09805955

申请日：2001-03-15

申请人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Yi Xu ,  Simon Chooi ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76826 ,  H01L21/31058 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829

摘要： This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

摘要翻译： 本发明涉及用于半导体集成电路器件的制造方法，更具体地说，涉及在双镶嵌互连中使用改进低介电常数有机材料之间的粘附性的交替蚀刻停止。 此外，蚀刻停止材料是含硅材料，并被转变成低介电常数材料（k = 3.5至5），其在UV辐射和甲硅烷基化之后变成富氧氧化硅，氧等离子体。

公开(公告)号：US06274499B1

公开(公告)日：2001-08-14

申请号：US09442493

申请日：1999-11-19

申请人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L21/76801 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.

摘要翻译： 根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。 在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。 介电覆盖层沉积在介电层上。 通孔被图案化并填充有金属层并且被平坦化。 沉积在平坦化的金属层和电介质盖层上的铜层。 铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。 在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。 介电覆盖层沉积在介电层上。 通过电介质盖层和电介质层形成双镶嵌开口。 将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。 将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

公开(公告)号：US06251786B1

公开(公告)日：2001-06-26

申请号：US09390783

申请日：1999-09-07

申请人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

发明人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

IPC分类号： H01L2100

CPC分类号： H01L21/76834 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

摘要翻译： 在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。 双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀 表面。

公开(公告)号：US06225202B1

公开(公告)日：2001-05-01

申请号：US09598689

申请日：2000-06-21

申请人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

发明人： Subhash Gupta ,  Mei-Sheng Zhou ,  Simon Chooi ,  Sangki Hong

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  C23F4/00 ,  H01L21/32136

摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.

摘要翻译： 描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。 在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。 在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。 在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。 半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。 将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

公开(公告)号：US06184138B2

公开(公告)日：2001-02-06

申请号：US09390782

申请日：1999-09-07

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.

摘要翻译： 提供了一种构建铜双镶嵌结构的新方法。 一层IMD沉积在衬底的表面上。 覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。 阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。 然后用镶嵌材料填充双镶嵌结构。 在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。 在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。 随后从双镶嵌结构中去除旋涂材料，并沉积铜。 仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。 使用上层CMP去除多余的铜。 如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。 作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。

公开(公告)号：US6040619A

公开(公告)日：2000-03-21

申请号：US937774

申请日：1997-09-25

申请人： Fei Wang ,  David K. Foote ,  Myron R. Cagan ,  Subhash Gupta

发明人： Fei Wang ,  David K. Foote ,  Myron R. Cagan ,  Subhash Gupta

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/312 ,  H01L21/314 ,  H01L21/318 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/11 ,  H01L29/78 ,  H01L23/58 ,  H01L21/316 ,  H01L23/48

CPC分类号： H01L21/0276 ,  H01L21/3121 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

摘要翻译： 在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。 用于器件的钨镶嵌互连使用具有大约40％至50％重量比的高硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。 蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。 蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。