公开(公告)号：US20090072290A1

公开(公告)日：2009-03-19

申请号：US11857770

申请日：2007-09-19

申请人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  William Tonti

发明人： Kangguo Cheng ,  Louis C. Hsu ,  Jack A. Mandelman ,  William Tonti

IPC分类号： H01L21/70 ,  H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L28/60

摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

摘要翻译： 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。

公开(公告)号：US07462547B2

公开(公告)日：2008-12-09

申请号：US11633380

申请日：2006-12-04

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Marwan Khater ,  Christopher M. Schnabel ,  William Tonti

IPC分类号： H01L21/331 ,  H01L27/082

CPC分类号： H01L29/66242 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0821

摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.

摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定 具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。

公开(公告)号：US20070252088A1

公开(公告)日：2007-11-01

申请号：US11380736

申请日：2006-04-28

申请人： Wagdi Abadeer ,  Ethan Cannon ,  Dennis Cox ,  William Tonti

发明人： Wagdi Abadeer ,  Ethan Cannon ,  Dennis Cox ,  William Tonti

IPC分类号： G01T1/02

CPC分类号： G01T1/244

摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.

摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

公开(公告)号：US20060252226A1

公开(公告)日：2006-11-09

申请号：US11485599

申请日：2006-07-12

申请人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/76

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

公开(公告)号：US20060249799A1

公开(公告)日：2006-11-09

申请号：US11481120

申请日：2006-07-05

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  David Fried ,  Robert Gauther ,  Edward Nowak ,  Jed Rankio ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  David Fried ,  Robert Gauther ,  Edward Nowak ,  Jed Rankio ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

公开(公告)号：US20060128071A1

公开(公告)日：2006-06-15

申请号：US10539333

申请日：2002-12-20

申请人： Jed Rankin ,  Wagdl Abadeer ,  Jeffrey Brown ,  William Tonti

发明人： Jed Rankin ,  Wagdl Abadeer ,  Jeffrey Brown ,  William Tonti

IPC分类号： H01L21/82

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/785

摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

摘要翻译： 描述了与半导体器件（例如FINFET或平面CMOS器件）集成的制造和反熔丝结构（100）的方法。 设置在设置在基板（10）上的绝缘体（3）上的半导体材料（11）的区域; 蚀刻工艺暴露了半导体材料中的多个拐角（111-114）。 露出的角部被氧化，以形成角落处的细长尖端（111t-114t）; 去除顶部上方的氧化物（31）。 然后在半导体材料上形成氧化物层（例如栅极氧化物），并覆盖在角部上; 该层在拐角处具有减小的厚度。 在角部处形成与氧化物层（51）接触的导电材料层（60），从而通过氧化物层在半导体材料和导电材料层之间形成多个可能的击穿路径。 将诸如老化电压的电压施加到结构将至少一个击穿路径转换成导电路径（103,280）。

公开(公告)号：US20050151213A1

公开(公告)日：2005-07-14

申请号：US10707746

申请日：2004-01-08

申请人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/00 ,  H01L27/14 ,  H01L29/82 ,  H01L31/058

CPC分类号： H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

摘要翻译： 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

公开(公告)号：US20050133884A1

公开(公告)日：2005-06-23

申请号：US11051703

申请日：2005-02-04

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20050125707A1

公开(公告)日：2005-06-09

申请号：US10729751

申请日：2003-12-04

申请人： Anthony Bonaccio ,  Michael LeStrange ,  William Tonti ,  Sebastian Ventrone

发明人： Anthony Bonaccio ,  Michael LeStrange ,  William Tonti ,  Sebastian Ventrone

IPC分类号： G06F1/04

CPC分类号： G06F1/04

摘要： An integrated circuit, including: a pulse generator adapted to generate a pulsed signal; a cycle counter adapted to count cycles of the pulsed signal; one or more repairable circuit elements; and a repair processor adapted to repair a repairable circuit element when the cycle counter reaches a pre-determined cycle count.

摘要翻译： 一种集成电路，包括：适于产生脉冲信号的脉冲发生器; 适于计数所述脉冲信号的周期的周期计数器; 一个或多个可修复电路元件; 以及修理处理器，其适于在循环计数器达到预定周期计数时修复可修复的电路元件。

公开(公告)号：US20050122160A1

公开(公告)日：2005-06-09

申请号：US10731298

申请日：2003-12-09

申请人： Wagdi Abadeer ,  Jennifer Appleyard ,  John Fifield ,  William Tonti

发明人： Wagdi Abadeer ,  Jennifer Appleyard ,  John Fifield ,  William Tonti

IPC分类号： G05F3/02 ,  G05F3/24

CPC分类号： G05F3/242

摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.

摘要翻译： 一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。