公开(公告)号：US20240395613A1

公开(公告)日：2024-11-28

申请号：US18794736

申请日：2024-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Sanghoon AHN ,  Woojin LEE ,  Kyung-Eun BYUN ,  Junghoo SHIN ,  Hyeonjin SHIN ,  Yunseong LEE

IPC: H01L21/768 ,  H01L21/285

Abstract: Provided is a method of forming an interconnect structure. The method includes preparing a substrate including a first metal layer and a first insulating layer, selectively forming a carbon layer having an sp2 bonding structure on the first metal layer, selectively forming a second insulating layer on the first insulating layer, forming a third insulating layer to cover the second insulating layer, and forming a second metal layer electrically connected to the first metal layer.

公开(公告)号：US20240186183A1

公开(公告)日：2024-06-06

申请号：US18441520

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Minhyun LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0259 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66045 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/78696

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

公开(公告)号：US20230349072A1

公开(公告)日：2023-11-02

申请号：US18193058

申请日：2023-03-30

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Taejin CHOI ,  Minsu KIM ,  Hyeonsuk SHIN ,  Hyeonjin SHIN

IPC: C30B29/40 ,  H01L27/146 ,  H01L29/78 ,  C30B29/60

CPC classification number: C30B29/40 ,  H01L27/1462 ,  H01L29/7851 ,  C30B29/605

Abstract: Disclosed is a nanocrystalline boron nitride film having a relatively low dielectric constant and excellent mechanical properties. The nanocrystalline boron nitride film includes a crystalline boron nitride compound, and has a dielectric constant within a range of 2.5 to 5.5 at a 100 kHz operating frequency.

公开(公告)号：US20230077783A1

公开(公告)日：2023-03-16

申请号：US18056446

申请日：2022-11-17

Applicant: Samsung Electronics Co.,Ltd

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/423

Abstract: A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

公开(公告)号：US20230076900A1

公开(公告)日：2023-03-09

申请号：US18055565

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20220320425A1

公开(公告)日：2022-10-06

申请号：US17836435

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd. ,  President and Fellows Of Harvard College

Inventor： Minhyun LEE ,  Dovran AMANOV ,  Renjing XU ,  Houk JANG ,  Haeryong KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Donhee HAM

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.

公开(公告)号：US20220319602A1

公开(公告)日：2022-10-06

申请号：US17708362

申请日：2022-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Taein KIM ,  Youngtek OH ,  Hyeonjin SHIN ,  Changseok LEE

IPC: G11C16/04 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578

Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

公开(公告)号：US20220302319A1

公开(公告)日：2022-09-22

申请号：US17495457

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Soonyong KWON ,  Junghwa KIM ,  Seungwoo SON ,  Seunguk SONG ,  Hyeonjin SHIN ,  Zonghoon LEE ,  Yeonchoo CHO

IPC: H01L29/786 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06

Abstract: Provided is a thin-film structure including a substrate, a nanocrystalline graphene layer provided on the substrate, and a two-dimensional material layer provided on the nanocrystalline graphene layer. The nucleation density of the two-dimensional material layer is 109 ea/cm2 or more according to the nanocrystalline graphene layer, and accordingly, a two-dimensional material layer having an improved uniformity may be formed and a time duration for forming the two-dimensional material layer may be greatly decreased.

公开(公告)号：US20220238721A1

公开(公告)日：2022-07-28

申请号：US17505955

申请日：2021-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Minsu SEOL ,  Eunkyu LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L29/786

Abstract: A semiconductor device according to an embodiment may include a substrate, an adhesive layer, and a semiconductor layer. The semiconductor layer includes a 2D material having a layered structure. The adhesive layer is interposed between the substrate and the semiconductor layer, and has adhesiveness to a 2D material.

公开(公告)号：US20220238692A1

公开(公告)日：2022-07-28

申请号：US17546303

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Van Luan NGUYEN ,  Minsu SEOL ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO ,  Yeonchoo CHO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/463

Abstract: A method of patterning a 2D material layer is includes selectively forming a first material layer on a surface of a substrate to form a first region in which the first material layer covers the surface of the substrate and to further form a second region in which the surface of the substrate is exposed from the first material layer, the first material layer having a strong adhesive force with a 2D material. The method further includes forming a 2D material layer is formed in both the first region and the second region. The method further includes selectively removing the 2D material layer from the second region based on using a physical removal method, such that the 2D material layer remains in the first region.