公开(公告)号：US20180033669A1

公开(公告)日：2018-02-01

申请号：US15225607

申请日：2016-08-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ali SALIH ,  Gordon M. GRIVNA

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L21/304 ,  H01L21/306 ,  H01L29/778 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/304 ,  H01L21/306 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/8258 ,  H01L23/3178 ,  H01L23/3192 ,  H01L24/95 ,  H01L27/0694 ,  H01L27/085 ,  H01L29/16 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/7816 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.

公开(公告)号：US20180025982A1

公开(公告)日：2018-01-25

申请号：US15644418

申请日：2017-07-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jefferson W. HALL ,  Gordon M. GRIVNA

IPC: H01L23/525 ,  G11C17/18 ,  G11C17/16

Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.

公开(公告)号：US20170352593A1

公开(公告)日：2017-12-07

申请号：US15478839

申请日：2017-04-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68309 ,  H01L2221/68327 ,  H01L2223/5446

Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces and a layer of material disposed along the second major surface. The method includes placing the wafer onto a carrier substrate and etching through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material. The method includes providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material. The method includes placing the wafer and the carrier substrate onto the support structure, and, in one embodiment, applying pressure and mechanical vibrations to the wafer to separate the layer of material in the singulation lines.

公开(公告)号：US20170125294A1

公开(公告)日：2017-05-04

申请号：US15403676

申请日：2017-01-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68336 ,  H01L2221/68381

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure.

公开(公告)号：US20170084705A1

公开(公告)日：2017-03-23

申请号：US15251984

申请日：2016-08-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L29/40 ,  H01L49/02

CPC classification number: H01L29/0649 ,  H01L21/76232 ,  H01L28/10 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/407 ,  H01L29/408 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include a substrate and an insulating structure laterally surrounded by the substrate. In an aspect, the electronic device can include a first conductive structure or an active region that is laterally surrounded by the insulating structure and the substrate. In another aspect, the electronic device can include an inductor surrounded by the insulating structure. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a plurality of features, including a first feature and a second feature, within the trench; forming a first insulating layer within the trench; removing the first feature to create a first cavity; forming a second insulating layer to at least partly fill the first cavity; removing the second feature to create a second cavity; and forming a conductive or semiconductor structure within the second cavity.

公开(公告)号：US20160343800A1

公开(公告)日：2016-11-24

申请号：US15225054

申请日：2016-08-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Michael J. SEDDON

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31144 ,  H01L21/78 ,  H01L21/784 ,  H01L25/0655 ,  H01L25/167 ,  H01L25/18 ,  H01L33/20 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

公开(公告)号：US20160005655A1

公开(公告)日：2016-01-07

申请号：US14849779

申请日：2015-09-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Michael J. SEDDON

IPC: H01L21/78 ,  H01L29/06 ,  H01L21/3065

CPC classification number: H01L29/06 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31144 ,  H01L21/78 ,  H01L21/784 ,  H01L25/0655 ,  H01L25/167 ,  H01L25/18 ,  H01L33/20 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Abstract translation: 在一个实施例中，形成具有各种不同形状的非矩形形状的半导体管芯和从半导体晶片切割的单元。

公开(公告)号：US20150332969A1

公开(公告)日：2015-11-19

申请号：US14808729

申请日：2015-07-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  B28D5/00 ,  H01L21/477 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683

CPC classification number: H01L21/78 ,  B28D5/0017 ,  H01L21/3065 ,  H01L21/477 ,  H01L21/67092 ,  H01L21/67098 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54453 ,  Y02P80/30 ,  Y10T29/41 ,  Y10T225/304 ,  Y10T225/379 ,  Y10T225/386

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.

Abstract translation: 在一个实施例中，通过将晶片放置在第一载体衬底上，使背面层与载体衬底相邻，将晶片放置在具有背层的晶片上，形成单晶线以暴露分离线内的背层，并使用 将局部压力施加到晶片以分离分离线中的背层的机械装置。 局部压力可以通过靠近背层的第一载体衬底施加，或者可以通过附接到与背层相对的晶片的前侧的第二载体衬底施加。

公开(公告)号：US20140264574A1

公开(公告)日：2014-09-18

申请号：US14168423

申请日：2014-01-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Gary H. LOECHELT ,  Gordon M. GRIVNA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66659 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835

Abstract: An electronic device can include different vertical conductive structures that can be formed at different times. The vertical conductive structures can have the same or different shapes. In an embodiment, an insulating spacer can be used to help electrically insulate a particular vertical conductive structure from another part of the workpiece, and an insulating spacer may not be used to electrically isolate a different vertical conductive structure. The vertical conductive structures can be tailored for particular electrical considerations or to a process flow when formation of other electronic components may also be formed within either or both of the particular vertical conductive structures.

Abstract translation: 电子设备可以包括可以在不同时间形成的不同的垂直导电结构。 垂直导电结构可具有相同或不同的形状。 在一个实施例中，可以使用绝缘间隔件来帮助将特定的垂直导电结构与工件的另一部分电绝缘，并且可以不使用绝缘间隔件来电隔离不同的垂直导电结构。 垂直导电结构可以针对特定的电学考虑或者在其它电子部件的形成也可以形成在特定的垂直导电结构中的任一个或两者内的过程流程。