公开(公告)号：US11984147B2

公开(公告)日：2024-05-14

申请号：US17602431

申请日：2020-04-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takanori Matsuzaki ,  Tatsuya Onuki ,  Yuki Okamoto ,  Toshiki Hamada

IPC: G11C11/405 ,  G11C11/4091 ,  G11C11/56 ,  H01L29/786

CPC classification number: G11C11/405 ,  G11C11/4091 ,  G11C11/5642 ,  G11C11/565 ,  H01L29/7869 ,  H01L29/78696 ,  G11C2211/5634

Abstract: A semiconductor device storing data as a multilevel potential is provided. The semiconductor device includes a memory cell, first and second reference cells, first and second sense amplifiers, and first to third circuits. The first circuit has a function of outputting, to a first wiring and a third wiring, a first potential corresponding to a first signal output from the memory cell. The second circuit has a function of outputting, to a second wiring, a first reference potential corresponding to a second signal output from the first reference cell. The third circuit has a function of outputting, to the fourth wiring, a second reference potential corresponding to a third signal output from the second reference cell when a second switch is in an off state. The first sense amplifier refers to the first potential and the first reference potential and changes potentials of the first wiring and the second wiring. The second sense amplifier refers to the first potential and the second reference potential and changes potentials of the third wiring and the fourth wiring.

公开(公告)号：US11935961B2

公开(公告)日：2024-03-19

申请号：US17284553

申请日：2019-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Eri Sato ,  Tatsuya Onuki ,  Yuto Yakubo ,  Hitoshi Kunitake

IPC: H03F3/45 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678

Abstract: A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

公开(公告)号：US11699465B2

公开(公告)日：2023-07-11

申请号：US17505110

申请日：2021-10-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: G11C5/06 ,  G11C11/4074 ,  H01L29/786 ,  G11C7/10 ,  H10B12/00 ,  G11C11/4091

CPC classification number: G11C5/063 ,  G11C7/1051 ,  G11C11/4074 ,  G11C11/4091 ,  H01L29/7869 ,  H10B12/30 ,  H10B12/50

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US11574945B2

公开(公告)日：2023-02-07

申请号：US16763024

申请日：2018-11-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Hajime Kimura ,  Shunpei Yamazaki

IPC: H01L27/12 ,  H01L27/146 ,  H01L27/105 ,  H01L29/786 ,  H04N5/3745

Abstract: An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

公开(公告)号：US11462538B2

公开(公告)日：2022-10-04

申请号：US16767645

申请日：2018-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Tomoaki Atsumi ,  Takahiko Ishizu

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.

公开(公告)号：US11379231B2

公开(公告)日：2022-07-05

申请号：US17074872

申请日：2020-10-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Tatsuya Onuki

IPC: G06F9/30 ,  G11C11/4094 ,  G11C11/402 ,  G11C11/408 ,  G11C11/4093

Abstract: To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.

公开(公告)号：US11205461B2

公开(公告)日：2021-12-21

申请号：US16625826

申请日：2018-06-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: G11C11/4091 ,  G11C7/10 ,  G11C5/06 ,  G11C11/4074 ,  H01L27/108 ,  H01L29/786

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US11195561B2

公开(公告)日：2021-12-07

申请号：US16764955

申请日：2018-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki Atsumi ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC: G11C7/04 ,  G11C5/04 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221 ,  G11C5/14

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US10860080B2

公开(公告)日：2020-12-08

申请号：US16476642

申请日：2018-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Maeda ,  Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato

IPC: G11C11/409 ,  G06F1/3234 ,  G11C5/14 ,  G11C14/00 ,  G11C16/30

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US09876495B2

公开(公告)日：2018-01-23

申请号：US15270047

申请日：2016-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C7/00 ,  H03K17/687 ,  H03K17/16 ,  H01L27/02 ,  H01L29/786

CPC classification number: H03K17/687 ,  H01L27/0207 ,  H01L29/78693 ,  H03K17/161 ,  H03K2217/0036

Abstract: A semiconductor device capable of reducing power consumption is provided. A writing potential is supplied to the cell 11 in which data rewriting is to be performed, whereby data is written. Meanwhile, in the cell 11 in which data rewriting is not to be performed, the data is transferred to the cell 12 and then the transferred data is rewritten to the cell 11. As a result, the data stored in the cell 11 in which data rewriting is not to be performed can be maintained without the reading and writing operation in a driver circuit. This results in a higher rewriting speed and lower power consumption in the driver circuit.