公开(公告)号：US09312349B2

公开(公告)日：2016-04-12

申请号：US14322555

申请日：2014-07-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tetsuhiro Tanaka ,  Takayuki Inoue ,  Yoshitaka Yamamoto ,  Hideomi Suzawa ,  Tamae Moriwaka

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/4234 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device in which the threshold value is controlled. Furthermore, to provide a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as a transistor is miniaturized can be suppressed. The semiconductor device includes a first semiconductor film, a source electrode and a drain electrode electrically connected to the first semiconductor film, a gate insulating film, and a gate electrode in contact with the gate insulating film. The gate insulating film includes a first insulating film and a trap film, and charge is trapped in a charge trap state in an interface between the first insulating film and the trap film or inside the trap film.

Abstract translation: 提供其中控制阈值的半导体器件。 此外，为了提供一种半导体器件，其中可以抑制作为晶体管变得更显着的电特性的劣化小型化。 半导体器件包括与栅极绝缘膜接触的第一半导体膜，与第一半导体膜电连接的栅极绝缘膜和栅电极的源电极和漏电极。 栅极绝缘膜包括第一绝缘膜和陷阱膜，并且在第一绝缘膜和陷阱膜之间的界面内或捕获膜内部的电荷陷阱状态下捕获电荷。

公开(公告)号：US09287117B2

公开(公告)日：2016-03-15

申请号：US14054078

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Tetsuhiro Tanaka

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/26

CPC classification number: H01L21/02565 ,  H01L21/02617 ,  H01L21/02631 ,  H01L27/1156 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a highly reliable semiconductor device including an oxide semiconductor by suppression of change in its electrical characteristics. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer and a gate insulating layer provided over the oxide semiconductor layer to a region where a channel is formed, whereby oxygen vacancies which might be generated in the channel are filled. Further, extraction of oxygen from the oxide semiconductor layer by a source electrode layer or a drain electrode layer in the vicinity of the channel formed in the oxide semiconductor layer is suppressed, whereby oxygen vacancies which might be generated in a channel are suppressed.

Abstract translation: 通过抑制其电特性的变化来提供包括氧化物半导体的高度可靠的半导体器件。 氧气由设置在氧化物半导体层下方的基底绝缘层和设置在氧化物半导体层上的栅极绝缘层提供到形成沟道的区域，从而填充可能在沟道中产生的氧空位。 此外，通过在氧化物半导体层中形成的沟道附近的源极电极层或漏极电极层从氧化物半导体层提取氧被抑制，由此抑制在沟道中可能产生的氧空位。

公开(公告)号：US09190527B2

公开(公告)日：2015-11-17

申请号：US14174412

申请日：2014-02-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki Tezuka ,  Hideomi Suzawa ,  Akihisa Shimomura ,  Tetsuhiro Tanaka

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02318 ,  H01L29/66969

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Oxygen is supplied from a base insulating layer provided below an oxide semiconductor layer to a channel formation region, whereby oxygen vacancies which might be generated in the channel formation region are filled. Further, a protective insulating layer containing a small amount of hydrogen and functioning as a barrier layer having a low permeability to oxygen is formed over the gate electrode layer so as to cover side surfaces of an oxide layer and a gate insulating layer that are provided over the oxide semiconductor layer, whereby release of oxygen from the gate insulating layer and/or the oxide layer is prevented and generation of oxygen vacancies in a channel formation region is prevented.

Abstract translation: 提供了包括氧化物半导体的高度可靠的半导体器件。 氧气从设置在氧化物半导体层下方的基底绝缘层供给到沟道形成区域，由此填充可能在沟道形成区域中产生的氧空位。 此外，在栅电极层上形成包含少量氢并用作具有低氧渗透性的阻挡层的保护绝缘层，以覆盖设置在氧化物层和栅绝缘层上的侧表面 氧化物半导体层，从而防止了从栅极绝缘层和/或氧化物层的氧的释放，并且防止了沟道形成区域中的氧空位的产生。

公开(公告)号：US09171959B2

公开(公告)日：2015-10-27

申请号：US14700528

申请日：2015-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Taiga Muraoka ,  Tetsuhiro Tanaka ,  Junichi Koezuka

IPC: H01L21/00 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

Abstract translation: 提供了一种具有稳定和高电特性并且高产率的小型化晶体管。 在包括依次层叠有氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管的半导体装置中，设置与栅电极层的侧面接触的第一侧壁绝缘层， 提供第二侧壁绝缘层以覆盖第一侧壁绝缘层的侧表面。 第一侧壁绝缘层是在其侧表面上形成具有均匀形状的缝隙的氧化铝膜。 第二侧壁绝缘层设置成覆盖缝隙。 源电极层和漏电极层设置成与氧化物半导体膜和第二侧壁绝缘层接触。

公开(公告)号：US09166021B2

公开(公告)日：2015-10-20

申请号：US14047639

申请日：2013-10-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki Tezuka ,  Tetsuhiro Tanaka ,  Toshihiko Takeuchi ,  Hideomi Suzawa ,  Suguru Hondo

IPC: H01L21/00 ,  H01L21/16 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78

Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Abstract translation: 为包括氧化物半导体的小型半导体器件提供稳定的电特性和高可靠性，并且制造半导体器件。 半导体器件包括基极绝缘层; 氧化物堆叠，其在所述基底绝缘层上方并且包括氧化物半导体层; 氧化层上的源电极层和漏电极层; 氧化层上的栅极绝缘层，源电极层和漏电极层; 栅绝缘层上的栅电极层; 以及在栅电极层上的层间绝缘层。 在半导体器件中，氧化物半导体层中的缺陷密度降低。

公开(公告)号：US09153436B2

公开(公告)日：2015-10-06

申请号：US14054162

申请日：2013-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hideomi Suzawa ,  Shinya Sasagawa ,  Tetsuhiro Tanaka

IPC: H01L21/00 ,  H01L21/02 ,  H01L29/04 ,  H01L29/26 ,  H01L29/78 ,  C23C14/08 ,  C23C14/34 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

Abstract translation: 在氧化物半导体层中包括沟道形成区域的半导体器件中，使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触并与氧化物半导体层接触的栅极绝缘膜供给氧 通过离子注入法引入的栅极绝缘膜到氧化物半导体层。

公开(公告)号：US20150179810A1

公开(公告)日：2015-06-25

申请号：US14575052

申请日：2014-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Akihisa Shimomura ,  Yasumasa Yamane ,  Yuhei Sato ,  Tetsuhiro Tanaka ,  Masashi Tsubuku ,  Toshihiko Takeuchi ,  Ryo Tokumaru ,  Mitsuhiro Ichijo ,  Satoshi Toriumi ,  Takashi Ohtsuki ,  Toshiya Endo

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract translation: 抑制了电特性的变化，并且提高了使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的氧化物半导体膜，绝缘表面上的抗氧化膜和氧化物半导体膜，与抗氧化膜接触的一对电极，一对电极上的栅极绝缘膜，以及栅极 电极，其在栅极绝缘膜上方并与氧化物半导体膜重叠。 在抗氧化剂膜中，与该对电极重叠的区域的宽度比不与该对电极重叠的区域的宽度长。

公开(公告)号：US09048321B2

公开(公告)日：2015-06-02

申请号：US13686332

申请日：2012-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Taiga Muraoka ,  Tetsuhiro Tanaka ,  Junichi Koezuka

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/66969

Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

公开(公告)号：US20150108472A1

公开(公告)日：2015-04-23

申请号：US14518259

申请日：2014-10-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hideomi Suzawa ,  Tetsuhiro Tanaka ,  Yuhei Sato ,  Sachiaki Tezuka ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/51

CPC classification number: H01L29/78648 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

Abstract translation: 提供具有高场效应迁移率的晶体管。 提供具有稳定电特性的晶体管。 提供了处于断开状态（非导通状态）的小电流的晶体管。 提供了包括这种晶体管的半导体器件。 第一电极形成在衬底上，第一绝缘层与第一电极的侧表面相邻地形成，并且形成第二绝缘层以覆盖第一绝缘层并与第一绝缘层的至少一部分表面接触 第一个电极。 第一电极的表面由不容易透过杂质元素的导电材料形成。 第二绝缘层由不容易透过杂质元素的绝缘材料形成。 在第一电极上形成氧化物半导体层，其间设置有第三绝缘层。

公开(公告)号：US08981370B2

公开(公告)日：2015-03-17

申请号：US13780325

申请日：2013-02-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro Tanaka ,  Erika Takahashi

IPC: H01L29/10 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device which has stable electrical characteristics and high reliability is provided. The semiconductor device includes a gate electrode over an insulating surface, a gate insulating film over the gate electrode, a semiconductor film which is over the gate insulating film and overlaps with the gate electrode, and a protective insulating film over the semiconductor film; and the protective insulating film includes a crystalline insulating film and an aluminum oxide film over the crystalline insulating film.

Abstract translation: 提供了具有稳定的电气特性和高可靠性的半导体器件。 半导体器件包括绝缘表面上的栅极电极，栅电极上的栅极绝缘膜，栅极绝缘膜上方并与栅电极重叠的半导体膜，以及半导体膜上的保护绝缘膜; 并且所述保护绝缘膜在所述结晶绝缘膜上包括结晶绝缘膜和氧化铝膜。