公开(公告)号：US20160293761A1

公开(公告)日：2016-10-06

申请号：US15180860

申请日：2016-06-13

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/161 ,  H01L27/12 ,  H01L29/165 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L27/1211 ,  G06N3/04 ,  G10L15/16 ,  H01L21/28132 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/365 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

公开(公告)号：US09460969B1

公开(公告)日：2016-10-04

申请号：US14669055

申请日：2015-03-26

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

Abstract: A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

Abstract translation: 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

公开(公告)号：US20160260741A1

公开(公告)日：2016-09-08

申请号：US15155904

申请日：2016-05-16

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Chun-Chen Yeh ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In forming a finFET, a selective nitridation process is used during spacer formation on the gate to support a finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract translation: 在形成finFET时，在栅极的间隔物形成期间使用选择性氮化工艺，以支持比使用传统间隔物沉积工艺可获得更细的翅片间距。 间隔物形成还可以允许对源极和漏极结的形成的精确控制。

公开(公告)号：US20160197072A1

公开(公告)日：2016-07-07

申请号：US15073100

申请日：2016-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

Abstract translation: 一种半导体器件，包括：衬底; 在第一半导体材料的衬底上方的第一组鳍; 在衬底上方的第二组鳍和不同于第一半导体材料的第二半导体材料; 以及位于所述第一和第二组翅片之间的隔离区域，所述隔离区域具有氮化物层。 隔离区可以是隔离柱或隔离沟槽。

公开(公告)号：US09385201B2

公开(公告)日：2016-07-05

申请号：US14297822

申请日：2014-06-06

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/84 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US20160190314A1

公开(公告)日：2016-06-30

申请号：US14588318

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US20160111513A1

公开(公告)日：2016-04-21

申请号：US14984688

申请日：2015-12-30

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是当金属用于形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分发生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US09318579B2

公开(公告)日：2016-04-19

申请号：US14300506

申请日：2014-06-10

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。

公开(公告)号：US09281382B2

公开(公告)日：2016-03-08

申请号：US14295618

申请日：2014-06-04

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-chen Yeh

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

公开(公告)号：US20150102410A1

公开(公告)日：2015-04-16

申请号：US14050666

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES INC ,  STMicroelectronics, Inc.

Inventor： QING LIU ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L29/66515 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/78684

Abstract: A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate.

Abstract translation: 制造半导体器件的方法可以包括在半导体层上形成栅极，在栅极附近形成侧壁间隔物，以及形成在栅极下方的半导体层中限定沟道的凸起的源极和漏极区域。 升高的源极和漏极区域可以通过侧壁间隔物与栅极间隔开。 该方法还可以包括移除侧壁间隔物以暴露凸起的源极和漏极区域和栅极之间的半导体层，并且形成覆盖栅极和升高的源极和漏极区域的应力层。 应力层可以接触凸起的源极和漏极区域与栅极之间的半导体层。