公开(公告)号：US06821870B2

公开(公告)日：2004-11-23

申请号：US10224468

申请日：2002-08-21

Applicant: Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

Inventor： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

IPC: H01L2122

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/66242

Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Abstract translation: 通过依次堆叠Si集电极层，SiGeC基极层和Si发射极层来制造异质结双极晶体管。 通过使Si集电体层的SiGeC基底层的晶格应变量为1.0％以下，带隙可以窄于现有实际SiGe的带隙（Ge含量为10％左右），良好 结晶可以在热处理后保持。 结果，可以实现没有实际麻烦的窄带隙基。

公开(公告)号：US06821856B2

公开(公告)日：2004-11-23

申请号：US10188108

申请日：2002-07-03

Applicant: Takeshi Takagi

Inventor： Takeshi Takagi

IPC: H01L21336

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78639

Abstract: A semiconductor device comprises an Si substrate, an isolation insulating film formed on the Si substrate, an Si layer formed on the Si substrate, a gate oxide film formed on the Si layer, a gate electrode formed on the gate oxide film, a sidewall formed on the side face of the gate electrode, a gate silicide film formed on the gate electrode, source and drain regions formed at both the sides of the gate electrode and including a part of the Si layer, and a silicide film formed on the source and drain regions. Because the source and drain regions are formed on a layer-insulating film so as to be overlayed, it is possible to decrease the active region and cell area of a device. Thereby, a high-speed operation and high integration can be realized.

Abstract translation: 半导体器件包括Si衬底，形成在Si衬底上的隔离绝缘膜，形成在Si衬底上的Si层，形成在Si层上的栅极氧化膜，形成在栅氧化膜上的栅电极，形成侧壁 在栅电极的侧面上，形成在栅电极上的栅极硅化物膜，形成在栅电极的两侧的源极和漏极区，并且包括一部分Si层，以及形成在源极上的硅化物膜 漏区。 因为源极和漏极区域形成在层间绝缘膜上以便被覆盖，所以可以减小器件的有源区域和单元面积。 由此，能够实现高速运转，高集成化。

公开(公告)号：US06642607B2

公开(公告)日：2003-11-04

申请号：US10061365

申请日：2002-02-04

Applicant: Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

Inventor： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC: H01L2993

CPC classification number: H01L29/93 ,  H01L27/0664 ,  H01L27/0808

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract translation: 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

公开(公告)号：US06492711B1

公开(公告)日：2002-12-10

申请号：US09598639

申请日：2000-06-21

Applicant: Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

Inventor： Takeshi Takagi ,  Koichiro Yuki ,  Kenji Toyoda ,  Yoshihiko Kanzawa

IPC: H01L27082

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/66242

Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

公开(公告)号：USD268371S

公开(公告)日：1983-03-22

申请号：US219721

申请日：1980-12-24

Applicant: Yonosuke Iwai ,  Takeshi Takagi

Designer： Yonosuke Iwai ,  Takeshi Takagi

公开(公告)号：USD250210S

公开(公告)日：1978-11-07

申请号：US785149

申请日：1977-04-06

Applicant: Takeshi Takagi ,  Hisatane Ohi ,  Yoshio Mizobata

Designer： Takeshi Takagi ,  Hisatane Ohi ,  Yoshio Mizobata

公开(公告)号：US09310342B2

公开(公告)日：2016-04-12

申请号：US13122602

申请日：2009-10-06

Applicant: Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi ,  Takuya Yotani ,  Makoto Takahara ,  Takayuki Oka

Inventor： Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi ,  Takuya Yotani ,  Makoto Takahara ,  Takayuki Oka

IPC: G01N30/24 ,  G01N30/26 ,  G01N30/20 ,  G01N30/88 ,  B01D15/16 ,  G01N30/74

CPC classification number: G01N30/24 ,  B01D15/16 ,  G01N30/26 ,  G01N30/34 ,  G01N30/74 ,  G01N2030/201 ,  G01N2030/202 ,  G01N2030/207 ,  G01N2030/8822

Abstract: A liquid chromatography apparatus is provided with a sample preparation unit, a column that separates components of a sample, an eluent supplier that includes a feeder for supplying eluents to the column, a flow path directional valve capable of introducing fixed amounts of the sample and the eluents to the column, an analyzer for analyzing a test solution composed of the sample components separated by the column and one of the eluents, and a controller, wherein the eluent supplier supplies the eluents to the flow path directional valve in an unmixed state. As a result of employing this configuration, analysis time is shortened and eluent consumption is reduced.

Abstract translation: 液相色谱装置具有样品制备单元，分离样品组分的柱，包括用于向柱供给洗脱液的供给器的洗脱液供给器，能够引入固定量的样品的流路切换阀和 用于分析由柱分离的样品组分和洗脱液之一组成的测试溶液的分析器和控制器，其中洗脱剂供体以未混合的状态将洗脱液供应到流路换向阀。 由于采用这种结构，分析时间缩短，洗脱液消耗减少。

公开(公告)号：US20140061579A1

公开(公告)日：2014-03-06

申请号：US13995383

申请日：2012-10-22

Applicant: Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

Inventor： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/145 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/15 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1625

Abstract: A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

Abstract translation: 可变电阻非易失性存储元件包括第一电极，第二电极和可变电阻层，包括：包含具有非化学计量组成的金属氧化物并包括p型载流子的第一氧化物层; 位于第一氧化物层之间并与第一氧化物层接触的第二氧化物层和第二电极，并且包括具有非化学计量组成并包括n型载体的金属氧化物; 位于所述第一氧化物层中的与第一电极没有接触并且氧含量原子百分比高于第一氧化物层的氧储存区; 以及位于所述第二氧化物层中的与氧储存区接触并且氧含量原子百分比低于第二氧化物层的原子百分比的局部区域。

公开(公告)号：US08619460B2

公开(公告)日：2013-12-31

申请号：US13509616

申请日：2011-10-26

Applicant: Yoshihiko Kanzawa ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0076 ,  G11C2213/56 ,  G11C2213/76

Abstract: A nonvolatile memory device (800) includes a variable resistance nonvolatile memory element (100) and a control circuit (810). The control circuit (810) determines whether a resistance value of the nonvolatile memory element (100) in a high resistance state is equal to or greater than a predetermined threshold value. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is smaller than the threshold value, the control circuit (810) applies a first voltage (VL1) to the nonvolatile memory element (100) to change a resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state. Moreover, if the resistance value of the nonvolatile memory element (100) in the high resistance state is equal to or greater than the threshold value, the control circuit (810) applies to the nonvolatile memory element (100) a second voltage (VL2) an absolute value of which is smaller an absolute value of the first voltage (VL1) to change the resistance state of the nonvolatile memory element (100) from the high resistance state to the low resistance state.

Abstract translation: 非易失性存储器件（800）包括可变电阻非易失性存储元件（100）和控制电路（810）。 控制电路（810）确定高电阻状态下的非易失性存储元件（100）的电阻值是否等于或大于预定阈值。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值小于阈值，则控制电路（810）向非易失性存储元件（100）施加第一电压（VL1） 非易失性存储元件（100）从高电阻状态到低电阻状态的电阻状态。 此外，如果高电阻状态下的非易失性存储元件（100）的电阻值为阈值以上，则控制电路（810）向非易失性存储元件（100）施加第二电压（VL2） 其绝对值对于将非易失性存储元件（100）的电阻状态从高电阻状态改变为低电阻状态的第一电压（VL1）的绝对值较小。

公开(公告)号：US08559205B2

公开(公告)日：2013-10-15

申请号：US13563321

申请日：2012-07-31

Applicant: Takumi Mikawa ,  Takeshi Takagi

Inventor： Takumi Mikawa ,  Takeshi Takagi

IPC: G11C17/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/115 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

Abstract: A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

Abstract translation: 一种非易失性半导体存储装置，包括基板，设置在基板上的下层电极布线，在与下层电极布线分别相对的位置设置有接触孔的层间绝缘层，分别与下层电极布线连接的电阻变化层， 层电极线; 以及分别设置在电阻变化层上的非欧姆器件。 非欧姆性器件各自具有包括多个半导体层的层压层结构，包括金属电极层和绝缘体层的层叠层结构，或者包括金属电极层和半导体层的层叠结构。 嵌入层叠层结构的一层以填充每个接触孔，作为层叠层结构的另一层的半导体层或绝缘体层的面积比每个接触孔的开口大， 设置在层间绝缘层上。