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    Multi-piece golf ball
    71.
    发明授权
    Multi-piece golf ball 有权
    多件高尔夫球

    公开(公告)号：US06565456B2

    公开(公告)日：2003-05-20

    申请号：US09778829

    申请日：2001-02-08

    申请人： Junji Hayashi ,  Rinya Takesue ,  Toshiaki Yamanaka

    发明人： Junji Hayashi ,  Rinya Takesue ,  Toshiaki Yamanaka

    IPC分类号： A63B3704

    CPC分类号： A63B37/02 ,  A63B37/0003 ,  A63B37/0043 ,  A63B37/0064 ,  A63B37/0065 ,  A63B37/0076 ,  A63B37/0092 ,  A63B2209/00

    摘要： In a multi-piece golf ball comprising a solid core, a surrounding layer, an intermediate layer, and a cover, at least one of the surrounding layer, the intermediate layer and the cover is formed of a heated mixture having a melt index of at least 1.0 dg/min and comprising (a) an olefin-carboxylic acid-optional carboxylate random copolymer and/or (d) a metal ion-neutralized olefin-carboxylic acid-optional carboxylate random copolymer; (b) a fatty acid or derivative; and (c) a neutralizing basic inorganic metal compound. The surrounding layer, the intermediate layer and the cover have a Shore D hardness of 10-55, 40-63 and 45-68, respectively, the hardness increasing in the order of surrounding layer, intermediate layer and cover. The ball is improved in feel, control, durability and flight performance.

    摘要翻译： 在包括实芯，周围层，中间层和盖的多片高尔夫球中，周围层，中间层和盖中的至少一个由熔体指数为at的加热混合物形成 至少1.0dg / min，并且包含（a）烯烃 - 羧酸任选的羧酸酯无规共聚物和/或（d）金属离子中和的烯烃 - 羧酸任选的羧酸酯无规共聚物; （b）脂肪酸或衍生物; 和（c）中和碱性无机金属化合物。 周围层，中间层和覆盖层的肖氏D硬度分别为10-55,40-63和45-68，硬度按照周围层，中间层和覆盖层的顺序增加。 球的感觉，控制，耐久性和飞行性能得到改善。

    Method of manufacturing semiconductor devices
    72.
    发明授权
    Method of manufacturing semiconductor devices 失效
    制造半导体器件的方法

    公开(公告)号：US06380085B2

    公开(公告)日：2002-04-30

    申请号：US09750061

    申请日：2000-12-29

    申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

    发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

    IPC分类号： H01L21302

    CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

    摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

    摘要翻译： 在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽 场区域和半导体衬底。 然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻部分地从存储垫部分去除绝缘膜。 在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。 能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。 同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使 可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

    Semiconductor integrated circuit device and process for manufacturing the same
    74.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06211004B1

    公开(公告)日：2001-04-03

    申请号：US09334266

    申请日：1999-06-16

    申请人： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    发明人： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    IPC分类号： H01L218234

    CPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

    摘要： A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

    摘要翻译： 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储器单元的驱动MISFET，传输MISFET和负载MISFET的栅电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。此外， 通过在第一导电层上叠置局部布线，在局部布线和第一导电层之间形成电容元件。此外，通过使用诸如硅化的电阻降低装置形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

    Semiconductor memory device having memory cells including IG FETs in a symmetrical arrangement
    80.
    发明授权
    Semiconductor memory device having memory cells including IG FETs in a symmetrical arrangement 失效
    具有存储单元的半导体存储器件包括对称布置的IG FET

    公开(公告)号：US5072286A

    公开(公告)日：1991-12-10

    申请号：US587974

    申请日：1990-09-25

    申请人： Masataka Minami ,  Shoji Shukuri ,  Mitsuru Hirao ,  Toshiaki Yamanaka

    发明人： Masataka Minami ,  Shoji Shukuri ,  Mitsuru Hirao ,  Toshiaki Yamanaka

    IPC分类号： H01L21/8244 ,  H01L27/11

    CPC分类号： H01L27/1112 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903

    摘要： A semiconductor memory device has memory cells each including first and second inverters cross-coupled to each other through first and second interconnecting conductors for forming a bistable circuit and first and second transfer gates connected between the first inverter and address signal conductors and between the second inverter and the address signal conductors, respectively. The first and second interconnecting conductors are arranged substantially point-symmetrically and have at least portions substantially parallel with each other on a surface of a substrate, and IG FETs constituting the first and second inverters have their gate electrodes arranged substantially parallel with one another and extending in a direction substantially perpendicular to the parallel portions of the first and second interconnecting conductors for the cross-coupling on the surface of the substrate.

    摘要翻译： 半导体存储器件具有各自包括通过第一和第二互连导体彼此交叉耦合以形成双稳态电路的第一和第二反相器的存储单元，以及连接在第一反相器和地址信号导体之间以及第二反相器之间的第一和第二传输门 和地址信号导体。 第一和第二互连导体基本上点对称地布置，并且在基板的表面上具有彼此基本平行的至少部分，并且构成第一和第二反相器的IG FET的栅电极彼此基本平行布置并且延伸 在基本上垂直于第一和第二互连导体的平行部分的方向上，用于在衬底表面上的交叉耦合。