公开(公告)号：US20080242016A1

公开(公告)日：2008-10-02

申请号：US12117232

申请日：2008-05-08

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。

公开(公告)号：US20080203492A1

公开(公告)日：2008-08-28

申请号：US12117371

申请日：2008-05-08

申请人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

发明人： Ethan Harrison Cannon ,  Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Jimmy Konstantinos Kontos ,  Jack Allan Mandelman ,  William Robert Tonti

IPC分类号： H01L27/092

CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

公开(公告)号：US20080137397A1

公开(公告)日：2008-06-12

申请号：US12019746

申请日：2008-01-25

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger

IPC分类号： G11C13/00 ,  H01L21/82 ,  G11C11/34

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/16 ,  G11C2213/77 ,  Y10S977/742 ,  Y10S977/939 ,  Y10S977/943

摘要： Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

摘要翻译： 使用垂直纳米管的非易失性和辐射硬的开关和存储器件，并通过范德华力力可逆地保持状态和制造器件的方法。 用于感测装置状态的装置包括测量电容，以及隧穿和场发射电流。

公开(公告)号：US06891235B1

公开(公告)日：2005-05-10

申请号：US09713830

申请日：2000-11-15

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Edward Joseph Nowak

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Edward Joseph Nowak

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/7833

摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.

摘要翻译： FET具有T形栅极。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。 因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。 两层被图案化在一起。 然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。 在另一个实施例中，栅极由单个栅极导体形成。 金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。 蚀刻硅化物以提供凹口。

公开(公告)号：US07027125B2

公开(公告)日：2006-04-11

申请号：US10808740

申请日：2004-03-25

申请人： Mark Charles Hakey ,  David Vaclay Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

发明人： Mark Charles Hakey ,  David Vaclay Horak ,  Charles William Koburger, III ,  Peter H. Mitchell

IPC分类号： G03B27/52 ,  G03B27/42

CPC分类号： G03F7/70808 ,  G03F7/70341

摘要： A photolithographic apparatus, system and method employing an improved refractive medium. The photolithographic apparatus may be used in an immersion lithography system for projecting light onto a workpiece such as a semiconductor wafer. In one embodiment, the photolithographic apparatus includes a container containing a transparent fluid. The fluid container is positioned between a lens element and the wafer. The container is further characterized as having a substantially flexible and transparent bottom membrane contacting an upper surface of the wafer and overlapping at least one side edge of the wafer such that a fluid filled skirt is formed extending beyond the edges of the wafer.

摘要翻译： 一种使用改进的折射介质的光刻设备，系统和方法。 光刻设备可以用于浸入式光刻系统中，用于将光投射到诸如半导体晶片的工件上。 在一个实施例中，光刻设备包括容纳透明流体的容器。 流体容器位于透镜元件和晶片之间。 该容器的特征还在于具有与晶片的上表面接触并且与晶片的至少一个侧边缘重叠的基本柔性且透明的底膜，从而形成延伸超过晶片边缘的充满液体的裙部。

公开(公告)号：US20080197448A1

公开(公告)日：2008-08-21

申请号：US12112549

申请日：2008-04-30

申请人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

发明人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

IPC分类号： H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

公开(公告)号：US07351648B2

公开(公告)日：2008-04-01

申请号：US11335372

申请日：2006-01-19

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chung Hon Lam

IPC分类号： H01L21/44 ,  H01L21/76

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76885

摘要： Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.

摘要翻译： 制造半导体器件的方法包括在下层上形成第一层，在第一层上形成硬掩模，以及通过硬掩模和第一层图形化孔。 形成在孔的侧面上延伸的突出端。 保形层沉积在悬垂孔和孔中，直到共形层封闭孔，以在每个孔中形成空隙/接缝。 每个孔中的空隙/接缝通过蚀刻顶部表面而暴露出来。 每个孔中的空隙/接缝延伸到下层。

公开(公告)号：US20080142995A1

公开(公告)日：2008-06-19

申请号：US12034901

申请日：2008-02-21

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger ,  Chung Hon Lam

IPC分类号： H01L23/48

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/528 ,  H01L2224/06 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

摘要翻译： 一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。 第一和第二结构被嵌套，使得亚光刻线以平行的方式设置在宽度内，并且第一结构的接触着陆段设置在相对于子平版印刷线的相对侧 第二结构的接触着陆段。 用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

公开(公告)号：US06342323B1

公开(公告)日：2002-01-29

申请号：US09523796

申请日：2000-03-13

申请人： William Hsioh-Lien Ma ,  David Vaclay Horak ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Mark Charles Hakey

发明人： William Hsioh-Lien Ma ,  David Vaclay Horak ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Mark Charles Hakey

IPC分类号： G03F900

CPC分类号： G03F9/7084 ,  G03F9/7046

摘要： An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

摘要翻译： 改进光刻对准方法。 在该方法中，第三级与两个先前级别对准，其中基于x和y方向上的两个先前级别来计算第三级的对准标记位置。 本发明的优选实施例涉及一种用于使半导体器件的第三级相对于器件的第一和第二级别对准的光刻对准方法。 该方法包括以下步骤：分别在第一和第二电平处形成第一和第二图案，以及确定两个原始方向上的第一和第二图案的偏移。 然后基于第一和第二图案的偏移的平均值来确定第三级中的第三图案的最佳位置。

公开(公告)号：US6066526A

公开(公告)日：2000-05-23

申请号：US12070

申请日：1998-01-22

申请人： Mark Charles Hakey ,  William Hsioh-Lien Ma

发明人： Mark Charles Hakey ,  William Hsioh-Lien Ma

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/10873

摘要： A process sequence for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The process sequence starts with deep trench (DT) processing, followed by deposition of insulator such as SiO2, planarization and pad strip. Then gate insulator and gate conductor are deposited. Also a pad or thin insulator can be deposited at this stage. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2. The gate conductor such as polysilicon is etched with a contact mask and reactive ion etching. If not previously deposited, a thin insulator is deposited. The structure is etched again with a gate poly contact mask. A gate conductor is then deposited. After a final etch, wiring is added.

摘要翻译： 用于八平方折叠位线动态随机存取存储器（DRAM）单元的处理顺序允许两个光刻特征的传输设备通道长度。 该方法使用没有间隔物限定特征的常规加工技术，并且使用常规结构。 工艺顺序从深沟（DT）处理开始，然后沉积诸如SiO 2，平坦化和焊盘条之类的绝缘体。 然后沉积栅极绝缘体和栅极导体。 在此阶段也可以沉积垫或薄绝缘体。 使用浅沟槽隔离掩模蚀刻该结构并填充SiO 2。 用接触掩膜和反应离子蚀刻蚀刻诸如多晶硅的栅极导体。 如果先前未沉积，则沉积薄的绝缘体。 用栅极聚接触掩模再次蚀刻该结构。 然后沉积栅极导体。 最终蚀刻后，加入接线。