公开(公告)号：US07324372B2

公开(公告)日：2008-01-29

申请号：US11507576

申请日：2006-08-22

申请人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Kiyoo Itoh ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： H01L27/101 ,  G11C7/12 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

摘要翻译： 本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

公开(公告)号：US07304910B1

公开(公告)日：2007-12-04

申请号：US11467793

申请日：2006-08-28

申请人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

IPC分类号： G11C8/18 ,  G11C5/14

CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。 在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时， 随后的突发读取周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

公开(公告)号：US07286430B2

公开(公告)日：2007-10-23

申请号：US11409238

申请日：2006-04-24

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C7/02

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

公开(公告)号：US07193884B2

公开(公告)日：2007-03-20

申请号：US11280170

申请日：2005-11-17

申请人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882

摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

公开(公告)号：US20070038919A1

公开(公告)日：2007-02-15

申请号：US11495550

申请日：2006-07-31

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C29/00

CPC分类号： G06F11/1044 ,  G11C2029/0409

摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

摘要翻译： 提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。 将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。 除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。 通过这种方式，可以更换制造过程中发生的错误。 此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。

公开(公告)号：US20060187720A1

公开(公告)日：2006-08-24

申请号：US11409238

申请日：2006-04-24

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C7/10

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

公开(公告)号：US07078273B2

公开(公告)日：2006-07-18

申请号：US10876461

申请日：2004-06-28

申请人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

发明人： Hideyuki Matsuoka ,  Kiyoo Itoh ,  Motoyasu Terao ,  Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： H01L21/82

CPC分类号： H01L27/2454 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

公开(公告)号：US07057912B2

公开(公告)日：2006-06-06

申请号：US10755333

申请日：2004-01-13

申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Riichiro Takemura

发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Riichiro Takemura

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： A T-CAM array is provided made up of ternary dynamic CAM cells each including a plurality of transistors. A refresh operation can be performed while reading out stored data to a match line using the same current path as that for a search operation, thereby providing a highly integrated array without reducing the original search speed. A rewrite data line is provided in parallel with a match line, and rewrite transistors are inserted between the rewrite data line and the storage nodes within each dynamic CAM cell. With this cell configuration, the data stored at each storage node is read out to the match line one at a time and rewritten through the rewrite data line to carry out a refresh operation.

公开(公告)号：US07054214B2

公开(公告)日：2006-05-30

申请号：US11009449

申请日：2004-12-13

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C7/02

CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

公开(公告)号：US07054200B2

公开(公告)日：2006-05-30

申请号：US10602885

申请日：2003-06-25

申请人： Satoru Hanzawa ,  Takeshi Sakata

发明人： Satoru Hanzawa ,  Takeshi Sakata

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/4074 ,  G11C11/4085

摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.