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    Method of operating a split gate flash memory cell with coupling gate
    71.
    发明授权
    Method of operating a split gate flash memory cell with coupling gate 有权
    操作具有耦合栅极的分离栅极闪存单元的方法

    公开(公告)号：US09245638B2

    公开(公告)日：2016-01-26

    申请号：US14216776

    申请日：2014-03-17

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

    IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  G11C16/14

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域中的第一和第二区域，设置在所述沟道区域和所述冷杉区域上方的浮置栅极，设置在所述沟道区域上方且横向邻近 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

    Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby
    72.
    发明授权
    Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby 有权
    制造具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元以及由此形成的存储单元的方法

    公开(公告)号：US09190532B2

    公开(公告)日：2015-11-17

    申请号：US14240440

    申请日：2012-08-08

    Applicant: Chunming Wang ,  Baowei Qiao ,  Zufa Zhang ,  Yi Zhang ,  Shiuh Luen Wang ,  Wen-Juei Lu

    Inventor： Chunming Wang ,  Baowei Qiao ,  Zufa Zhang ,  Yi Zhang ,  Shiuh Luen Wang ,  Wen-Juei Lu

    IPC: H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833

    Abstract: A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.

    Abstract translation: 非易失性存储单元具有具有顶表面的第一导电类型的单晶衬底。 第二导电类型的第一区域沿着顶表面在衬底中。 第二导电类型的第二区域沿着顶表面在与第一区域间隔开的衬底中。 通道区域是第一区域和第二区域。 字线门位于与第一区域紧邻的沟道区域的第一部分上方。 字线栅极通过第一绝缘层与沟道区间隔开。 浮动栅极位于通道区域的另一部分上。 浮栅具有通过第二绝缘层与沟道区分离的下表面和与下表面相对的上表面。 浮栅具有与字线门相邻但与字线门隔开的第一侧壁; 以及与第一侧壁相对的第二侧壁。 第二侧壁和上表面形成锋利的边缘，第二侧壁的长度大于第一侧壁。 上表面从第一侧壁向上倾斜到第二侧壁。 耦合栅极位于浮动栅极的上表面上方，并通过第三绝缘层与其隔离。 擦除栅极位于浮动栅极的第二侧壁附近。 擦除栅极定位在第二区域上并与之绝缘。

    Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same
    73.
    发明授权
    Passive elements, articles, packages, semiconductor composites, and methods of manufacturing same 有权
    被动元件，制品，封装，半导体复合材料及其制造方法

    公开(公告)号：US08846538B1

    公开(公告)日：2014-09-30

    申请号：US13560915

    申请日：2012-07-27

    Applicant: Bomy Chen ,  Long Ching Wang ,  Sychi Fang

    Inventor： Bomy Chen ,  Long Ching Wang ,  Sychi Fang

    IPC: H01L21/302

    CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5389 ,  H01L28/10 ,  H01L28/91 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.

    Abstract translation: 公开了与半导体制品相关联的系统和方法，包括在衬底上形成第一材料层，在限定第一层中的无源元件的区域内蚀刻沟槽，在沟槽的侧壁上形成金属区域，以及形成电介质区域 聚合物材料在衬底上或衬底中。 此外，示例性方法还可以包括在沟槽的侧壁上形成金属区域的区域，使得这些区域的平面条带部分形成无源元件的导电区域，该无源元件相对于主要平面基本上垂直地排列 底物。 其它示例性实施例可以包括与本文所阐述的创新的一个或多个方面一致的各种物品或方法，包括电容和/或感应方面，基于钛和/或钽的电阻方面，产品，通过工艺，封装和复合材料的产品。

    Non-volatile memory device and a method of operating same
    74.
    发明授权
    Non-volatile memory device and a method of operating same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US08811093B2

    公开(公告)日：2014-08-19

    申请号：US13419269

    申请日：2012-03-13

    Applicant: Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: G11C16/04

    CPC classification number: G11C16/04 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418

    Abstract: An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.

    Abstract translation: 在第一导电类型的半导体衬底中的非易失性存储单元阵列。 每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。 字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。 耦合栅极覆盖浮栅。 擦除门覆盖第二区域。 位线连接到第一区域。 负电荷泵电路产生负电压。 控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

    Method of forming a memory cell by reducing diffusion of dopants under a gate
    76.
    发明授权
    Method of forming a memory cell by reducing diffusion of dopants under a gate 有权
    通过减少栅极下掺杂剂的扩散形成存储单元的方法

    公开(公告)号：US08785307B2

    公开(公告)日：2014-07-22

    申请号：US13593448

    申请日：2012-08-23

    Applicant: Xian Liu ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    Inventor： Xian Liu ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

    IPC: H01L21/04

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

    Abstract translation: 形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极 一侧的浮动门。 在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于 九十度，大于零度。

    Method of operating a split gate flash memory cell with coupling gate
    78.
    发明授权
    Method of operating a split gate flash memory cell with coupling gate 有权
    操作具有耦合栅极的分离栅极闪存单元的方法

    公开(公告)号：US08711636B2

    公开(公告)日：2014-04-29

    申请号：US13463558

    申请日：2012-05-03

    Applicant: Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'Mani

    Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'Mani

    IPC: G11C16/04

    CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

    Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

    Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。

    Method Of Forming A Memory Cell By Reducing Diffusion Of Dopants Under A Gate
    79.
    发明申请
    Method Of Forming A Memory Cell By Reducing Diffusion Of Dopants Under A Gate 有权
    通过减少门下掺杂剂的扩散形成存储单元的方法

    公开(公告)号：US20140057422A1

    公开(公告)日：2014-02-27

    申请号：US13593448

    申请日：2012-08-23

    Applicant: XIAN LIU ,  MANDANA TADAYONI ,  CHIEN-SHENG SU ,  NHAN DO

    Inventor： XIAN LIU ,  MANDANA TADAYONI ,  CHIEN-SHENG SU ,  NHAN DO

    IPC: H01L21/04

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.

    Abstract translation: 形成存储单元的方法包括在衬底上形成导电浮栅，在浮置栅极上形成导电控制栅极，在浮栅的一侧横向形成导电擦除栅极，并横向形成导电选择栅极 一侧的浮动门。 在形成浮置和选择栅极之后，该方法包括使用注入工艺将掺杂剂注入到选择栅极下方的沟道区域的一部分中，所述注入工艺以相对于衬底表面小于 九十度，大于零度。

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