公开(公告)号：US20150067310A1

公开(公告)日：2015-03-05

申请号：US14281657

申请日：2014-05-19

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Terry Parks ,  Darius D. Gaskins

IPC分类号： G06F9/44

CPC分类号： G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

摘要： A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

摘要翻译： 微处理器包括多个处理核心和配置寄存器，配置寄存器被配置为指示多个处理核心中的每一个是启用还是禁用。 所述多个处理核心中的每一个启用的一个处理核心被配置为在第一情况下读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于配置寄存器的读取生成相应的配置相关值 一审。 配置寄存器被更新以指示多个处理核心中先前启用的一个处理核心被禁用。 所述多个处理核心中的每一个被配置为在第二实例中读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于对配置寄存器的读取生成相应的配置相关值 第二例。

公开(公告)号：US20150067250A1

公开(公告)日：2015-03-05

申请号：US14281585

申请日：2014-05-19

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F12/08

CPC分类号： G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

摘要： A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.

摘要翻译： 微处理器包括多个处理核心，由多个处理核心共享的资源以及由非结构化地址空间内的多个处理核心中的每一个可读和写的硬件信号量。 多个处理核心中的每一个被配置为写入硬件信号量以请求所有权共享资源并从硬件信号量读取以确定是否获得所有权。 多个处理核心中的每一个被配置为写入硬件信号量以放弃共享资源的所有权。

公开(公告)号：US20150058610A1

公开(公告)日：2015-02-26

申请号：US13972657

申请日：2013-08-21

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Dinesh K. Jain

IPC分类号： G06F9/44

CPC分类号： G06F9/4403

摘要： An apparatus including a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is programmed with compressed configuration data for the each of the plurality of cores. The second plurality of semiconductor fuses is programmed with core designation data that associates some of the compressed configuration data with one of the plurality of cores, where the one of the plurality of cores accesses and decompresses the some of the compressed configuration data upon power-up/reset, for initialization of elements within the one of the plurality of cores.

公开(公告)号：US20150058565A1

公开(公告)日：2015-02-26

申请号：US13972741

申请日：2013-08-21

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Dinesh K. Jain

IPC分类号： G06F3/06 ,  G11C17/16

CPC分类号： G06F15/177 ,  G11C17/16 ,  G11C29/785

摘要： An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.

公开(公告)号：US20150058563A1

公开(公告)日：2015-02-26

申请号：US13972358

申请日：2013-08-21

申请人： VIA TECHNOLOGIES, INC.

发明人： G. Glenn Henry ,  Dinesh K. Jain

IPC分类号： G06F3/06 ,  G11C17/16 ,  G06F12/08

CPC分类号： G06F15/177 ,  G06F12/0802 ,  G11C17/16 ,  G11C29/785

摘要： An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

摘要翻译： 设想用于在多核微处理器中存储和解压缩配置数据的装置。 该装置包括共享熔丝阵列和多个微处理器核。 共享保险丝阵列设置在管芯上并且包括用压缩配置数据编程的多个半导体保险丝。 多个微处理器核心也设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化内部的元件 多个核心中的每一个。 多个核心中的每一个具有复位控制器，其被配置为解压缩所有压缩的配置数据，并且分发解压缩的配置数据以初始化元件。

公开(公告)号：US08963930B2

公开(公告)日：2015-02-24

申请号：US11954621

申请日：2007-12-12

申请人： Yang (Jeff) Jiao ,  Mike Hong ,  Yin Li ,  Yunjie Xu

发明人： Yang (Jeff) Jiao ,  Mike Hong ,  Yin Li ,  Yunjie Xu

IPC分类号： G06T1/00 ,  G06T15/00

CPC分类号： G06T15/005

摘要： A system for integrating triangle setup and attribute setup operations into a programmable execution unit of a graphics processing unit is disclosed. A method for integrating triangle setup and attribute setup operations into a programmable execution unit graphics processing unit is also disclosed. In one embodiment, at least one execution unit is configured for multi-threaded operation. The at least one execution unit is configured to execute at least one thread for triangle setup operations and attribute setup operations as well as threads for pixel shader, geometry shader and vertex shader operations.

摘要翻译： 公开了一种用于将三角形设置和属性设置操作集成到图形处理单元的可编程执行单元中的系统。 还公开了一种将三角形设置和属性设置操作集成到可编程执行单元图形处理单元中的方法。 在一个实施例中，至少一个执行单元被配置用于多线程操作。 所述至少一个执行单元被配置为执行用于三角形设置操作和属性设置操作的至少一个线程以及用于像素着色器，几何着色器和顶点着色器操作的线程。

公开(公告)号：US20150042666A1

公开(公告)日：2015-02-12

申请号：US14159169

申请日：2014-01-20

申请人： VIA TECHNOLOGIES, INC.

发明人： Chien-Cheng SUNG ,  Ping-Huei HSIEH

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G09G5/006 ,  G09G5/363 ,  G09G2370/042 ,  G09G2370/047 ,  G09G2370/14

摘要： An image transmission apparatus for providing a low voltage differential signaling (LVDS) data stream to a display panel is provided. The image transmission apparatus includes a transmitter and a graphic processing unit (GPU). The transmitter obtains an extended display identification data (EDID) according to an inter integrated circuit signal from the display panel. The GPU provides configuration data according to the EDID, and provides a display port (DP) data stream according to an image data. The transmitter obtains a transfer parameter according to the configuration data, and converts the DP data stream into the LVDS data stream according to the transfer parameter.

摘要翻译： 提供一种用于向显示面板提供低电压差分信号（LVDS）数据流的图像传输装置。 图像传输装置包括发射机和图形处理单元（GPU）。 发射机根据来自显示面板的集成电路信号获得扩展显示识别数据（EDID）。 GPU根据EDID提供配置数据，并根据图像数据提供显示端口（DP）数据流。 发射机根据配置数据获取传输参数，并根据传输参数将DP数据流转换为LVDS数据流。

公开(公告)号：US08952662B2

公开(公告)日：2015-02-10

申请号：US13351130

申请日：2012-01-16

申请人： Chun-Chen Ma

发明人： Chun-Chen Ma

IPC分类号： H02J7/00

CPC分类号： H02J7/0016 ,  H02J7/0021

摘要： A battery control circuit for balancing a battery includes a voltage detector, a controller, a balancing device, and a switch. The voltage detector is configured to detect a voltage difference of the battery so as to generate a detecting signal. The controller is configured to generate a control signal according to the detecting signal. The switch is coupled between the battery and the balancing device, and is opened or closed according to the control signal, wherein if the voltage difference is greater than a threshold value, the switch is closed and the balancing device draws a load current from the battery, and if the voltage difference is smaller than or equal to the threshold value, the switch is opened and the balancing device is not capable of drawing any current.

摘要翻译： 用于平衡电池的电池控制电路包括电压检测器，控制器，平衡装置和开关。 电压检测器被配置为检测电池的电压差，以产生检测信号。 控制器被配置为根据检测信号产生控制信号。 开关耦合在电池和平衡装置之间，并且根据控制信号被打开或关闭，其中如果电压差大于阈值，则开关闭合，并且平衡装置从电池抽取负载电流 ，如果电压差小于或等于阈值，则开关断开，平衡装置不能吸取任何电流。

公开(公告)号：US08928377B2

公开(公告)日：2015-01-06

申请号：US13951295

申请日：2013-07-25

申请人： VIA Technologies, Inc.

发明人： Imran Qureshi

IPC分类号： H03K3/00 ,  H03K3/356

CPC分类号： H03K3/356104 ,  G06F2207/3872 ,  H03K19/017581

摘要： A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.

摘要翻译： 一种可扫描的快速动态寄存器，包括数据和扫描使能电路，预充电电路，选择电路，存储电路和扫描输入使能电路。 在正常模式下，数据和扫描使能电路响应于评估时钟，将第一预充电节点拉到放电节点。 预充电电路对第一和第二预充电节点进行预充电，其中一个预充电节点根据数据块的评估而放电。 存储电路和输出门响应于第二预充电节点以提供输出。 选择电路插在存储电路之前，以允许以扫描模式注入扫描数据。 在扫描模式下，扫描输入使能电路将扫描数据提供给选择和存储电路。 扫描输入使能电路还包括存储电路，其以第一存储电路在主从配置中操作。

公开(公告)号：US08909908B2

公开(公告)日：2014-12-09

申请号：US12582975

申请日：2009-10-21

申请人： Rodney E. Hooker ,  Gerard M. Col ,  Bryan Wayne Pogor

发明人： Rodney E. Hooker ,  Gerard M. Col ,  Bryan Wayne Pogor

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3806 ,  G06F9/3861

摘要： A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.

摘要翻译： 流水线式无序执行按顺序退出微处理器包括预测分支指令的目标地址的分支预测器，取得预测目标地址的指令的获取单元，以及执行单元，其解析目标地址 分支指令，并检测预测和解决的目标地址不同; 响应于检测到预测和解析的目标地址不同，确定是否存在必须被校正并且在程序顺序中比分支指令更旧的未命令指令; 通过刷新在预测目标地址处获得的指令来执行分支指令，并且如果不存在必须被校正并且在程序顺序中比分支指令更老的指令，则从解决的目标地址获取提取单元; 否则，不执行分支指令。