公开(公告)号：US20120273888A1

公开(公告)日：2012-11-01

申请号：US13547717

申请日：2012-07-12

申请人： Serguei OKHONIN

发明人： Serguei OKHONIN

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L27/1203 ,  G11C7/00 ,  G11C11/40 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1207 ,  H01L29/7841

摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region, and a gate is disposed over a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion.

摘要翻译： 描述了包括其的电路的半导体器件及其操作方法。 该装置包括电浮体区域，并且栅极设置在身体区域的第一部分之上。 该装置包括与该区域的第二部分邻接的源极区域，该第二部分与该第一部分相邻并且将该源区域与该第一部分分开。 该装置包括与该区域的第三部分邻接的漏极区域，该第三部分与该第一部分相邻并且将该漏极区域与该第一部分分开。

公开(公告)号：US20120268159A1

公开(公告)日：2012-10-25

申请号：US13416098

申请日：2012-03-09

申请人： Yong Min Cho ,  Dong-Ryul Lee

发明人： Yong Min Cho ,  Dong-Ryul Lee

IPC分类号： G01R31/26

CPC分类号： G11C29/022 ,  G01R31/2884 ,  G01R31/307 ,  G11C11/40 ,  G11C2029/5002 ,  H01L22/30 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of detecting a defect of a semiconductor device includes forming test patterns and unit cell patterns in a test region a cell array region of a substrate, respectively, obtaining reference data with respect to the test patterns by irradiating an electron beam into the test region, obtaining cell data by irradiating the electron beam into the cell array region, and detecting defects of the unit cell patterns by comparing the obtained cell data with the obtained reference data.

摘要翻译： 检测半导体器件的缺陷的方法包括分别在基板的单元阵列区域的测试区域中形成测试图案和单元格图案，通过将电子束照射到测试区域中来获得关于测试图案的参考数据 通过将电子束照射到单元阵列区域来获得单元数据，并且通过将获得的单元数据与获得的参考数据进行比较来检测单元单元图案的缺陷。

公开(公告)号：US08107314B2

公开(公告)日：2012-01-31

申请号：US12360621

申请日：2009-01-27

申请人： Kota Hara

发明人： Kota Hara

IPC分类号： G11C8/00

CPC分类号： G11C29/48 ,  G11C7/20 ,  G11C7/22 ,  G11C11/40 ,  G11C11/401 ,  G11C11/40615 ,  G11C11/4072 ,  G11C29/08 ,  G11C29/1201

摘要： A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.

公开(公告)号：US08081506B2

公开(公告)日：2011-12-20

申请号：US12637358

申请日：2009-12-14

申请人： Charles C. Kuo ,  Derchang Kau

发明人： Charles C. Kuo ,  Derchang Kau

IPC分类号： G11C11/00

CPC分类号： G11C11/40 ,  G11C13/0004 ,  G11C14/009 ,  G11C2213/15 ,  H01L27/2436 ,  H01L45/04

摘要： A voltage memory switch may be formed of an amorphous semiconductor threshold switch and a select device. The amorphous threshold switch may be latched into one of two different current conducting levels. Then, in some embodiments, a relatively dense memory array can be achieved by maintaining an appropriate bias on the cell to prevent it from losing the programmed state.

摘要翻译： 电压存储器开关可以由非晶半导体阈值开关和选择器件形成。 非晶态阈值开关可以被锁存在两个不同的电流传导电平之一中。 然后，在一些实施例中，可以通过在单元上保持适当的偏置来防止其失去编程状态来实现相对密集的存储器阵列。

公开(公告)号：US20110249488A1

公开(公告)日：2011-10-13

申请号：US13108156

申请日：2011-05-16

申请人： Werner Juengling

发明人： Werner Juengling

IPC分类号： G11C11/24 ,  H01L21/28 ,  G11C11/00

CPC分类号： G11C11/40 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

摘要翻译： 公开了一种方法和装置，其中包括具有第一栅极的第一半导体鳍片，与第一半导体鳍片相邻并具有第二栅极的第二半导体鳍片和在第一半导体鳍片与第二半导体鳍片之间延伸的第三栅极的器件 半导体鳍片 在一些实施例中，第三栅极可以不与第一栅极或第二栅极电连接。

公开(公告)号：US07388238B2

公开(公告)日：2008-06-17

申请号：US11452275

申请日：2006-06-14

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/10

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20060244007A1

公开(公告)日：2006-11-02

申请号：US11477249

申请日：2006-06-28

申请人： Arup Bhattacharyya

发明人： Arup Bhattacharyya

IPC分类号： H01L29/74

CPC分类号： H01L27/108 ,  G11C11/40 ,  G11C11/404 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.

公开(公告)号：US20050243613A1

公开(公告)日：2005-11-03

申请号：US11174859

申请日：2005-07-05

申请人： Tah-Kang Joseph Ting ,  Shih-Hsing Wang ,  Hong-Jie Chen

发明人： Tah-Kang Joseph Ting ,  Shih-Hsing Wang ,  Hong-Jie Chen

IPC分类号： G11C5/00 ,  H01L21/66

CPC分类号： G01R31/31922 ,  G11C11/40 ,  G11C29/006 ,  G11C29/023 ,  G11C2029/5602

摘要： A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

公开(公告)号：US20050121664A1

公开(公告)日：2005-06-09

申请号：US11035786

申请日：2005-01-13

申请人： Tsu-Jae King

发明人： Tsu-Jae King

IPC分类号： G11C11/40 ,  H01L31/0336

CPC分类号： G11C11/40 ,  G11C2211/5614

摘要： A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

公开(公告)号：US06651196B1

公开(公告)日：2003-11-18

申请号：US09504795

申请日：2000-02-15

申请人： Akihiro Iwase ,  Yoshiharu Kato

发明人： Akihiro Iwase ,  Yoshiharu Kato

IPC分类号： G01R313181

CPC分类号： G11C29/40 ,  G01R31/31701 ,  G11C11/40 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/0407

摘要： A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

摘要翻译： 半导体器件具有正常工作模式和测试模式。 决定电路确定设备是否进入测试模式。 当输入测试模式时，控制电路改变与正常操作模式有关的信息。 如果意外输入测试模式，则由于与正常操作有关的信息已经改变，用户可以容易地确定设备已进入测试模式。