公开(公告)号：US20100327409A1

公开(公告)日：2010-12-30

申请号：US12864091

申请日：2009-01-22

申请人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/92 ,  H01L21/314

CPC分类号： H01L28/60 ,  H01L21/28506 ,  H01L21/31637 ,  H01L21/32053 ,  H01L21/32105 ,  H01L23/5223 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0688 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.

摘要翻译： 形成在半导体器件内的电容元件包括上电极，含有过渡金属元素的氧化物和/或硅酸盐的电容绝缘膜，以及具有多晶导电膜的下电极，所述多晶导体膜由比所述转变 金属元素和形成在多晶导电膜下面的非晶或微晶导电膜。

公开(公告)号：US07834458B2

公开(公告)日：2010-11-16

申请号：US12638022

申请日：2009-12-15

申请人： Hui-Lin Chang ,  Hung Chun Tsai ,  Yung-Cheng Lu ,  Syun-Ming Jang

发明人： Hui-Lin Chang ,  Hung Chun Tsai ,  Yung-Cheng Lu ,  Syun-Ming Jang

IPC分类号： H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

摘要翻译： 提供了形成在第一介电层中的铜互连结构的盖层。 在一个实施例中，盖层可以通过原位沉积工艺形成，其中引入包含锗，砷，钨或镓的工艺气体，从而形成铜 - 金属帽层。 在另一个实施例中，提供铜 - 金属硅化物帽。 在该实施方案中，在引入工艺气体之前，期间或之后引入硅烷，该工艺气体包括锗，砷，钨或镓。 此后，可以形成可选的蚀刻停止层，并且可以在蚀刻停止层或第一介电层上方形成第二介电层。

公开(公告)号：US20090020829A1

公开(公告)日：2009-01-22

申请号：US12175450

申请日：2008-07-17

申请人： Aditi CHANDRA ,  Arvind KAMATH ,  James Montague CLEEVES ,  Joerg ROCKENBERGER ,  Mao Takashima ,  Erik SCHER

发明人： Aditi CHANDRA ,  Arvind KAMATH ,  James Montague CLEEVES ,  Joerg ROCKENBERGER ,  Mao Takashima ,  Erik SCHER

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/288 ,  H01L21/28518 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/78618 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.

摘要翻译： 公开了使用包含硅化物形成金属的油墨形成触点（和任选的局部互连）的方法，诸如二极管和/或包括这种触点的晶体管的电气器件，（可选的）局部互连）以及用于形成这种器件的方法。 形成接触的方法包括将硅化物形成金属的油墨沉积到暴露的硅表面上，干燥油墨以形成形成硅化物的金属前体，以及加热形成硅化物的金属前体和硅表面以形成金属硅化物 联系。 任选地，可以将金属前体油墨选择性地沉积到与暴露的硅表面相邻的电介质层上，以形成含金属互连。 此外，一个或多个体导电金属可以沉积在剩余的金属前体油墨和/或介电层上。 可以使用这种印刷的接触和/或局部互连来制造电子器件，例如二极管和晶体管。 金属墨水可以同时印刷以用于接触以及局部互连，或者替代地，如果需要用于接触和互连线的不同金属，印刷金属可以用作其它金属的无电沉积的种子 。 这种方法有利地减少了处理步骤的数量，并且不一定需要任何蚀刻。

公开(公告)号：US07442593B2

公开(公告)日：2008-10-28

申请号：US11480912

申请日：2006-07-06

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时，例如，栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US20080179748A1

公开(公告)日：2008-07-31

申请号：US12079683

申请日：2008-03-28

申请人： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

发明人： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

IPC分类号： H01L23/52

CPC分类号： H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

公开(公告)号：US20080179653A1

公开(公告)日：2008-07-31

申请号：US11936339

申请日：2007-11-07

申请人： Tatsuya FUKUMURA ,  Yoshihiro Ikeda ,  Shunichi Narumi ,  Izumi Takesue

发明人： Tatsuya FUKUMURA ,  Yoshihiro Ikeda ,  Shunichi Narumi ,  Izumi Takesue

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11517 ,  G11C16/0433 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/768 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42376

摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.

摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。

公开(公告)号：US07288473B2

公开(公告)日：2007-10-30

申请号：US11294455

申请日：2005-12-06

申请人： Hyoung-Yoon Kim

发明人： Hyoung-Yoon Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76829 ,  H01L21/32053 ,  H01L21/76825 ,  H01L21/76855 ,  H01L21/76886

摘要： Canting or falling of an upper metal line may be prevented by improving adhesion between an insulation layer and a metal layer. A method for forming a semiconductor which improves adhesion between an insulation layer and a metal layer includes: preparing a substrate formed with a lower metal layer; forming an insulation layer on the substrate; forming a plug after etching the insulation layer; performing a silicon ion implantation process from above the insulation layer; forming an upper metal layer on the insulation layer, the upper metal layer having a bottom layer of a Ti layer or a TiN layer; and siliciding a predetermined region of the bottom layer of the upper metal layer by heat treatment of the substrate.

摘要翻译： 可以通过改善绝缘层和金属层之间的粘合力来防止上金属线的放置或落下。 一种改善绝缘层和金属层之间的粘附性的半导体的方法包括：制备形成有下金属层的衬底; 在所述基板上形成绝缘层; 在蚀刻绝缘层之后形成插头; 从绝缘层上方进行硅离子注入工艺; 在所述绝缘层上形成上金属层，所述上金属层具有Ti层或TiN层的底层; 并且通过所述基板的热处理将所述上金属层的底层的预定区域硅化。

公开(公告)号：US20070120222A1

公开(公告)日：2007-05-31

申请号：US11600105

申请日：2006-11-16

申请人： Hiroyuki Ode

发明人： Hiroyuki Ode

IPC分类号： H01L29/00 ,  H01L21/465 ,  C23F1/00

CPC分类号： H01L21/02301 ,  B08B7/0021 ,  C23C18/04 ,  C23C18/1204 ,  H01L21/02057 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/02181 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31645 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76841

摘要： This invention provides a method for manufacturing a semiconductor silicon substrate by use of carbon dioxide in a supercritical state, which method is capable of making the semiconductor silicon substrate highly reliable one. Specifically, this invention provides a method for manufacturing a semiconductor silicon substrate including at least two of: a cleaning step of cleaning a substrate to be treated in a presence of carbon dioxide in a supercritical state; a film forming step of forming at least one of a conducting film, an insulating film and barrier film on the substrate to be treated in the presence of carbon dioxide in the supercritical state; an etching step of etching the substrate to be treated in the presence of carbon dioxide in the supercritical state; and a resist removing step of removing a resist on the substrate to be treated in the presence of carbon dioxide in the supercritical state.

摘要翻译： 本发明提供一种通过使用超临界状态的二氧化碳制造半导体硅衬底的方法，该方法能够使半导体硅衬底高度可靠。 具体地说，本发明提供一种制造半导体硅衬底的方法，该方法至少包括以下两个步骤：在超临界状态的二氧化碳存在下清洁待处理衬底的清洁步骤; 在超临界状态的二氧化碳的存在下在待处理的基板上形成导电膜，绝缘膜和阻挡膜中的至少一个的成膜步骤; 在超临界状态的二氧化碳的存在下蚀刻待处理的基板的蚀刻步骤; 以及抗蚀剂除去步骤，在超临界状态的二氧化碳的存在下除去待处理基板上的抗蚀剂。

公开(公告)号：US07091520B2

公开(公告)日：2006-08-15

申请号：US10265105

申请日：2002-10-07

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L29/10

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时，例如，栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US07041584B2

公开(公告)日：2006-05-09

申请号：US10867765

申请日：2004-06-16

申请人： Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshitaka Tsunashima ,  Takayuki Ito ,  Kyoichi Suguro

发明人： Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshitaka Tsunashima ,  Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/324 ,  H01L21/335

CPC分类号： H01L21/324 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76886 ,  H01L29/665

摘要： An aspect of the present invention provides a method of manufacturing a semiconductor device, including, forming an insulating film on a silicide layer formed at the surface of a silicon semiconductor substrate, etching the insulating film to form a contact hole in which the silicide layer is exposed, forming a metal nitride film on the bottom and side wall of the contact hole, carrying out a first heating process at 600° C. or lower on the substrate, carrying out, during the first heating process, a second heating process for 10 msec or shorter with light whose main wavelength is shorter than a light absorbing end of silicon, forming a contact conductor in the contact hole after the second heating process, and forming, on the insulating film, wiring that is electrically connected to the substrate through the contact conductor.