公开(公告)号：US09473097B2

公开(公告)日：2016-10-18

申请号：US14515342

申请日：2014-10-15

Applicant: STMicroelectronics SA

Inventor： Emmanuel Rouat

IPC: H03F1/34 ,  H03G3/30 ,  H03F3/45 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/30 ,  H03F3/45071 ,  H03F2203/45178 ,  H03F2203/45202 ,  H03F2203/45336 ,  H03F2203/45528 ,  H03G1/0088 ,  H03G3/001

Abstract: A resistive ladder has first, second and third resistors coupled in series between first and second voltage terminals. A first node of the first resistor is coupled to the first voltage terminal and a first node of the third resistor is coupled to the second voltage terminal. A voltage selection unit has a first input coupled to a first node of the second resistor and a second input coupled to a second node of the second resistor and is adapted to selectively couple one of the first and second inputs to an output node of said resistive ladder. The resistive ladder also includes a first switch coupled between a second node of the third resistor and the second voltage terminal.

Abstract translation: 电阻梯具有在第一和第二电压端子之间串联耦合的第一，第二和第三电阻器。 第一电阻器的第一节点耦合到第一电压端子，并且第三电阻器的第一节点耦合到第二电压端子。 电压选择单元具有耦合到第二电阻器的第一节点的第一输入和耦合到第二电阻器的第二节点的第二输入，并且适于选择性地将第一和第二输入中的一个耦合到所述电阻的输出节点 阶梯。 电阻梯还包括耦合在第三电阻器的第二节点和第二电压端子之间的第一开关。

公开(公告)号：US09464933B1

公开(公告)日：2016-10-11

申请号：US14920373

申请日：2015-10-22

Applicant: STMicroelectronics SA

Inventor： Hani Sherry

IPC: G01J1/42 ,  G01J1/44

CPC classification number: G01J1/4228 ,  G01J1/42 ,  G01J1/44 ,  H03K3/0315

Abstract: The present disclosure concerns a high frequency imager including a pixel matrix, each pixel including a high frequency oscillator, a transmission line positioned at a distance from an active surface of the imager smaller than the operating wavelength of the oscillator, a first end of the line being coupled to the oscillator, and a read circuit coupled to a second end of the line.

Abstract translation: 本公开涉及包括像素矩阵的高频成像器，每个像素包括高频振荡器，位于与成像器的有源表面相距一定距离处的传输线小于振荡器的工作波长，线的第一端 耦合到所述振荡器，以及耦合到所述线路的第二端的读取电路。

公开(公告)号：US09461641B2

公开(公告)日：2016-10-04

申请号：US14062455

申请日：2013-10-24

Applicant: STMicroelectronics SA

Inventor： Severin Trochut ,  Emilie Rigal ,  Fabrice Blisson ,  Frederic Hasbani ,  Nicolas Seller

IPC: H03K17/687 ,  H03K17/22 ,  G06F1/32

CPC classification number: H03K17/6871 ,  G06F1/3287 ,  H03K17/22 ,  Y02D10/171 ,  Y10T307/76

Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.

Abstract translation: 一连串的开关连接在耦合到第一电压的第一电源线和耦合到扇区的第二电源线之间。 这些开关由控制信号控制。 控制信号从第一链的第一端传播到第一链的第二端，而在该第一次传播期间不控制开关。 然后，控制信号从第二端朝向第一端的相反方向传播，在第二次传播期间通过位于第二端的一组至少一个开关的一组开关进行控制。 在反向传播结束时，检测到链的第一端处的控制信号的到达。

公开(公告)号：US20160284807A1

公开(公告)日：2016-09-29

申请号：US14930324

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Frederic Monsieur ,  Xavier Federspiel ,  Gregory Bidal

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/127 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/7838

Abstract: A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.

Abstract translation: 绝缘体上硅型的衬底由绝缘体上硅型的初始衬底形成，其中半导体膜位于位于载体衬底顶部的掩埋绝缘层本身的顶部上。 制造半导体膜的厚度的局部修改以便形成在不同区域中具有不同厚度的半导体膜。

公开(公告)号：US09455689B2

公开(公告)日：2016-09-27

申请号：US14547684

申请日：2014-11-19

Applicant: STMICROELECTRONICS SA ,  UNIVERSITY OF TWENTE

Inventor： Andreia Cathelin ,  Bram Nauta

IPC: H01L21/8238 ,  H01L29/66 ,  H03K3/012 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC classification number: H03K3/012 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78648

Abstract: A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

Abstract translation: 硅绝缘体电流源阵列包括用于接收控制电压的输入控制，用于接收第一参考电压的第一参考输入和用于接收第二参考电压的第二参考输入。 具有相同类型的多个绝缘体硅MOS晶体管的链条具有全部连接到输入控制的控制电极，第一导电电极全部连接到第一参考输入，第二导电电极分别连接到第二参考输入 当在输入控制上施加控制电压时，当几个晶体管导通时，多个负载电路分别被配置为被几个电流穿过。 输入偏置耦合到位于晶体管链下方的绝缘掩埋层下方的半导体阱，用于接收偏置电压差。

公开(公告)号：US09430592B2

公开(公告)日：2016-08-30

申请号：US13689997

申请日：2012-11-30

Applicant: STMicroeletronics SA

Inventor： Jean-Robert Manouvrier

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5009 ,  G06F17/5036

Abstract: A method for simulating, in an electrical device simulator, electrical behavior of an integrated diode is described. The diode is modelled using a compact model in the electrical device simulator to determine the electrical behavior of the diode in a given situation. The modelling includes modelling a series resistance relating to the active regions and to the connections, modelling a PN junction of the diode, and modelling a well resistance for positive values of a current passing through the diode involving a conductivity modulation model. The method further includes modelling of the well resistance for negative values of the current by a curve which increases steeply from an initial resistance value corresponding to a zero value of current up to a plateau.

Abstract translation: 描述了在电气设备模拟器中模拟集成二极管的电气行为的方法。 在电气设备模拟器中使用紧凑型模型对二极管进行建模，以确定给定情况下二极管的电气行为。 该建模包括对与有源区和连接相关的串联电阻进行建模，对二极管的PN结进行建模，以及对通过涉及电导率调制模型的二极管的电流的正值对阱电阻建模。 该方法还包括通过由对应于电流零值直到平稳的初始电阻值急剧上升的曲线来模拟电流负值的电流值。

公开(公告)号：US09423580B2

公开(公告)日：2016-08-23

申请号：US14637559

申请日：2015-03-04

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Estelle Batail

IPC: G02F1/01 ,  G02F1/035 ,  G02F1/295 ,  G02B6/12 ,  G02B6/10 ,  G02B6/42 ,  G02B6/13 ,  H01L21/768 ,  H01L49/02 ,  G02F1/025 ,  H01L27/02

CPC classification number: G02B6/4275 ,  G02B6/13 ,  G02F1/025 ,  G02F2202/22 ,  H01L21/768 ,  H01L27/0248 ,  H01L28/40

Abstract: An ESD protection device for an electro-optical device may include an optical waveguide segment being in semiconductor material and including a central zone of a first conductivity type, and first and second wings of a second conductivity type different from the first conductivity type and being integral with the central zone. The ESD protection device may include a first conduction terminal on the first wing for defining a first protection terminal, a second conduction terminal on the second wing for defining a second protection terminal, and a resistive contact structure of the first conductivity type having a transverse arm integral with the central zone, and an end in ohmic contact with the first conduction terminal, the resistive contact structure being electrically insulated from the first wing.

Abstract translation: 用于电光装置的ESD保护装置可以包括半导体材料中的光波导段，并且包括第一导电类型的中心区，以及不同于第一导电类型的第二导电类型的第一和第二翼， 与中央区。 ESD保护装置可以包括在第一翼上的用于限定第一保护端子的第一导电端子，用于限定第二保护端子的第二机翼上的第二导电端子，以及具有横臂的第一导电类型的电阻接触结构 与中心区域成一体，并且与第一导电端子欧姆接触的端部，电阻接触结构与第一机翼电绝缘。

公开(公告)号：US09407204B2

公开(公告)日：2016-08-02

申请号：US14219716

申请日：2014-03-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Vincent Heinrich ,  Bruno Paille

IPC: H04K1/10 ,  H04L27/28 ,  H03D3/06 ,  H04L27/144 ,  H04L27/16

CPC classification number: H03D3/06 ,  H04L27/144 ,  H04L27/16

Abstract: A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results.

Abstract translation: 公开了一种用于处理调频模拟信号的方法和相应装置。 信号包括属于一组M个符号的符号的数目，分别与一组M个频率的至少一个频率相关联。 该方法包括读取信号的每个符号的相位，其包括对应于符号的持续时间的信号部分的采样，并且递送N个采样（M小于N）。 对N个样本执行M个离散傅立叶变换处理操作。 每个单独的处理操作与每个频率相关联。 M个人处理操作提供M个处理结果。 可以从M处理结果确定符号的值。

公开(公告)号：US09405137B2

公开(公告)日：2016-08-02

申请号：US14283340

申请日：2014-05-21

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert Manouvrier

IPC: G02F1/025 ,  G02F1/225 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/12 ,  G02F1/2257 ,  H04B10/548

Abstract: A semiconductor electro-optical phase shifter may include an optical action zone configured to be inserted in an optical waveguide, and a bipolar transistor structure configured so that, in operation, collector current of the bipolar transistor structure crosses the optical action zone perpendicular to the axis of the optical waveguide.

公开(公告)号：US20160197048A1

公开(公告)日：2016-07-07

申请号：US15070046

申请日：2016-03-15

Applicant: STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-Francois Carpentier

IPC: H01L23/66 ,  H01Q19/10 ,  H01L23/528 ,  H04B1/3827 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01Q13/10 ,  H01L23/522

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A three-dimensional integrated structure includes a support element, an interface device connected to the support element by a first electrically conductive connection, and an integrated circuit arranged between the support element and the interface device and connected to the interface device by a second electrically conductive connection. A filler region is positioned between the second electrically conductive connection and between the interface device and the integrated circuit. An antenna is distributed over the interface device and the integrated circuit and has a radiating element electromagnetically coupled with an excitation element through the interconnection of a slot.

Abstract translation: 三维集成结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，以及布置在支撑元件和接口装置之间并且通过第二导电连接到接口装置的集成电路 连接。 填充区域位于第二导电连接之间以及接口装置和集成电路之间。 天线分布在接口装置和集成电路上，并且具有通过插槽的互连与激励元件电磁耦合的辐射元件。