公开(公告)号：US20080283897A1

公开(公告)日：2008-11-20

申请号：US11857978

申请日：2007-09-19

Applicant: Yu-Sheng Ding ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Yu-Sheng Ding ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28061 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/7887

Abstract: The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance.

Abstract translation: 本发明提供一种闪存器件及其制造方法。 该器件包括形成在衬底上的栅极电介质层和栅极多晶硅层的栅极堆叠层，包括形成在栅极堆叠层的侧壁上的浮置多晶硅层和栅极间隔区的堆叠层。 在栅叠层上形成金属层，代替栅极多晶硅层的一部分。 因为金属层具有较高的导电性并且电连接到稍后形成的金属塞上，因此提高了器件的电流速度以提高性能。

公开(公告)号：US20080265302A1

公开(公告)日：2008-10-30

申请号：US11955397

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract translation: 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US20080095411A1

公开(公告)日：2008-04-24

申请号：US11603031

申请日：2006-11-22

Applicant: Wen-Liang Hwang ,  Jian-Liang Lin ,  Chung-Lin Huang ,  Wei-Gang Che

Inventor： Wen-Liang Hwang ,  Jian-Liang Lin ,  Chung-Lin Huang ,  Wei-Gang Che

IPC: G06K9/00

CPC classification number: G06K9/0061

Abstract: The present invention disclose an iris recognition method, which utilizes a matching pursuit algorithm to simplify the extraction and reconstruction of iris features and reduce the memory space required by each iris feature vector without the penalty of recognition accuracy. The iris recognition method of the present invention comprises an iris-localization component and a pattern matching component. The iris-localization component locates the iris region via the color difference between different portions of the eyeball. The primary iris features are extracted from iris information and transformed into a sequence of iris feature vectors by a matching pursuit algorithm. Thus, the iris image can be represented by a sequence of atoms, and each atom contains base, amplitude and location. Then, the comparison between the feature vectors of two irises is performed to determine whether the two irises match.

Abstract translation: 本发明公开了一种虹膜识别方法，其利用匹配追踪算法来简化虹膜特征的提取和重建，并减少每个虹膜特征向量所需的存储空间，而不会损失识别精度。 本发明的虹膜识别方法包括虹膜定位部件和图案匹配部件。 虹膜定位组件经由眼球的不同部分之间的色差定位虹膜区域。 主要虹膜特征从虹膜信息中提取，并通过匹配追踪算法转换成虹膜特征向量序列。 因此，虹膜图像可以由原子序列表示，并且每个原子包含基底，幅度和位置。 然后，执行两个虹膜的特征向量之间的比较，以确定两个虹膜是否匹配。

公开(公告)号：US07323743B2

公开(公告)日：2008-01-29

申请号：US11603771

申请日：2006-11-22

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US07115477B2

公开(公告)日：2006-10-03

申请号：US10884769

申请日：2004-07-02

Applicant: Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L29/512 ,  H01L21/26506 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583

Abstract: A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.

Abstract translation: 具有双栅介质层的栅极及其制造方法。 提供半导体衬底，其上依次形成介电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 离子注入半导体衬底，去除间隔物和暴露的电介质层，并且在开口的底部形成栅极氧化物层。

公开(公告)号：US07005701B2

公开(公告)日：2006-02-28

申请号：US10318551

申请日：2002-12-13

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L29/76 ,  H01L39/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract translation: 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06916715B2

公开(公告)日：2005-07-12

申请号：US10694155

申请日：2003-10-27

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/148

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract translation: 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06893919B2

公开(公告)日：2005-05-17

申请号：US10810740

申请日：2004-03-26

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

公开(公告)号：US06847068B2

公开(公告)日：2005-01-25

申请号：US10441801

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/8242

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.

公开(公告)号：US06815290B2

公开(公告)日：2004-11-09

申请号：US10457867

申请日：2003-06-10

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.