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92 条记录 (耗时 0.023 秒)

    Integrated Circuit Having a Fin Structure
    82.
    发明申请
    Integrated Circuit Having a Fin Structure 失效
    具有鳍结构的集成电路

    公开(公告)号：US20080308856A1

    公开(公告)日：2008-12-18

    申请号：US11762582

    申请日：2007-06-13

    申请人： Michael Specht ,  Franz Hofmann ,  Wolfgang Roesner ,  Guerkan Ilicali

    发明人： Michael Specht ,  Franz Hofmann ,  Wolfgang Roesner ,  Guerkan Ilicali

    IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L29/792

    CPC分类号： H01L27/115 ,  H01L25/0657 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66818 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.

    摘要翻译： 本发明的实施例一般涉及用于制造集成电路的方法，用于制造单元布置的方法，集成电路，单元布置和存储器模块。 在本发明的一个实施例中，提供一种用于制造具有单元布置的集成电路的方法，包括形成至少一个半导体鳍结构，其具有用于多个鳍场效应晶体管的面积，其中每个鳍场效应晶体管的面积 包括具有第一鳍结构宽度的第一区域，具有第二鳍结构宽度的第二区域，其中第二鳍结构宽度小于第一鳍结构宽度。 此外，在半导体鳍片结构的第二区域上或上方形成多个电荷存储区域。

    Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module
    83.
    发明申请
    Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module 审中-公开
    集成电路，电池，电池布置，集成电路的制造方法，电池的制造方法，存储器模块

    公开(公告)号：US20080237694A1

    公开(公告)日：2008-10-02

    申请号：US11728960

    申请日：2007-03-27

    申请人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L29/513

    摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.

    摘要翻译： 本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。 在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一 高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

    Charge-trapping memory cell and method for production
    84.
    发明授权
    Charge-trapping memory cell and method for production 有权
    电荷俘获记忆体和生产方法

    公开(公告)号：US07298004B2

    公开(公告)日：2007-11-20

    申请号：US11000350

    申请日：2004-11-30

    申请人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

    发明人： Michael Specht ,  Wolfgang Roesner ,  Franz Hofmann

    IPC分类号： H01L29/788

    CPC分类号： H01L21/76895 ,  H01L21/28282 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/792

    摘要： The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

    摘要翻译： 存储单元阵列包括多个平行翅片，它们设置成彼此相距约40nm的位线，并且具有小于约30nm的横向尺寸，被细分成相邻的第一和第二鳍片对。 鳍片上布置有电荷俘获记忆层序列。 词汇排列在翅片之间，源极/漏极区域位于字线之间的翅片和翅片的末端。 优选地，在鳍片的端部处的源极/漏极区域的自对准接触区域，每个接触区域对于所述成对中的一个的翅片是共同的。 选择晶体管，并且单独地为第一和第二散热片提供选择线以使得能够单独寻址存储器单元。

    Method for the production of a memory cell, memory cell and memory cell arrangement
    85.
    发明授权
    Method for the production of a memory cell, memory cell and memory cell arrangement 有权
    用于生产存储器单元，存储单元和存储单元布置的方法

    公开(公告)号：US07195978B2

    公开(公告)日：2007-03-27

    申请号：US10999810

    申请日：2004-11-29

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Michael Specht

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Michael Specht

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    摘要： Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located essentially in a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, a channel region located between the two source/drain regions, wherein the channel region at least partly laterally overlaps the floating gate and the read gate electrode.

    摘要翻译： 具有辅助基板的存储单元，其上形成有第一栅极绝缘层，形成在第一栅极绝缘层上的浮动栅极，形成在浮动栅极上的电绝缘层，形成在电绝缘层上的存储栅电极， 基板固定到存储栅电极，第二栅极绝缘层，形成在辅助基板的表面的一部分上，该表面通过部分去除辅助基板而被覆盖，形成在第二栅极绝缘层上的读取栅电极和两个 源极/漏极区域基本上位于辅助衬底的不含第二栅极绝缘层和读取栅电极的剩余材料的表面区域中，位于两个源极/漏极区域之间的沟道区域，其中沟道区域在 至少部分地侧向重叠浮置栅极和读取栅电极。

    Semiconductor memory component
    86.
    发明申请
    Semiconductor memory component 失效
    半导体存储器组件

    公开(公告)号：US20060267082A1

    公开(公告)日：2006-11-30

    申请号：US11438883

    申请日：2006-05-23

    申请人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    发明人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    IPC分类号： H01L29/76

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

    摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。