公开(公告)号：US20140215240A1

公开(公告)日：2014-07-31

申请号：US14227680

申请日：2014-03-27

Applicant: Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/32

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US08645728B2

公开(公告)日：2014-02-04

申请号：US13461956

申请日：2012-05-02

Applicant: Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F15/00

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。

公开(公告)号：US20130311738A1

公开(公告)日：2013-11-21

申请号：US13996438

申请日：2012-03-30

Applicant: Xiaowei Jiang ,  Hongliang Gao ,  Zhen Fang ,  Srihari Makineni ,  Ravishankar Iyer

Inventor： Xiaowei Jiang ,  Hongliang Gao ,  Zhen Fang ,  Srihari Makineni ,  Ravishankar Iyer

IPC: G06F12/14

CPC classification number: G06F12/1466 ,  G06F12/1027 ,  G06F12/126

Abstract: An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.

Abstract translation: 描述了一种装置，其包含处理核心，其包括CPU核心和耦合到CPU核心的至少一个加速器。 CPU核心包括具有翻译旁边缓冲器的管线。 CPU核心包括逻辑电路，用于在转换后备缓冲器条目中的条目的属性数据中设置锁定位，以锁定为加速器保留的存储器页面。

公开(公告)号：US20130262902A1

公开(公告)日：2013-10-03

申请号：US13992361

申请日：2011-09-06

Applicant: Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadogopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadogopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/5094 ,  G06F12/084 ,  G06F13/24 ,  G06F2212/1028 ,  G06F2212/60 ,  G06F2212/62 ,  H04W52/028 ,  H04W88/02 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/22 ,  Y02D70/00

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从加速器接收中断的方法，响应于该中断将恢复信号直接发送到小型核心，并向第一小型核心提供大型核心的执行状态的子集，以及 确定小型核心是否可以处理与该中断有关的请求，如果该确定是肯定的，则执行与该小核心中的该请求相对应的操作，否则将大的核心执行状态和恢复信号提供给该大核心 。 描述和要求保护其他实施例。

公开(公告)号：US20130185370A1

公开(公告)日：2013-07-18

申请号：US13810033

申请日：2012-01-13

Applicant: Bin Li ,  Li Zhao ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal

Inventor： Bin Li ,  Li Zhao ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal

IPC: H04L12/58

CPC classification number: H04L51/04 ,  G06F13/4022 ,  G06F2213/0038 ,  H04L49/109 ,  H04L51/30

Abstract: Methods and apparatus for efficient peer-to-peer communication support in interconnect fabrics. Network interfaces associated with agents are implemented to facilitate peer-to-peer transactions between agents in a manner that ensures data accesses correspond to the most recent update for each agent. This is implemented, in part, via use of non-posted “dummy writes” that are sent from an agent when the destination between write transactions originating from the agent changes. The dummy writes ensure that data corresponding to previous writes reach their destination prior to subsequent write and read transactions, thus ordering the peer-to-peer transactions without requiring the use of a centralized transaction ordering entity.

Abstract translation: 互连结构中有效的对等通信支持的方法和设备。 实现与代理相关联的网络接口以便于以确保数据访问对应于每个代理的最新更新的方式促进代理之间的对等事务。 这部分是通过使用从代理发出的写入事务之间的目标之间从代理发送的未发布的“虚拟写入”来实现的。 虚拟写入确保与之前的写入相对应的数据在后续写入和读取事务之前到达其目的地，从而排序对等事务，而不需要使用集中式事务排序实体。

公开(公告)号：USD673194S1

公开(公告)日：2012-12-25

申请号：US29397042

申请日：2011-07-11

Applicant: Jeffrey F. Kovac ,  Lewis Ray Morrison ,  Kumar Reddy Mylavaram Nikhilesh ,  Ravishankar Iyer

Designer： Jeffrey F. Kovac ,  Lewis Ray Morrison ,  Kumar Reddy Mylavaram Nikhilesh ,  Ravishankar Iyer

公开(公告)号：US20120284486A1

公开(公告)日：2012-11-08

申请号：US13550966

申请日：2012-07-17

Applicant: Zhen Fang ,  Mahesh Wagh ,  Jasmin Ajanovic ,  Michael E. Espig ,  Ravishankar Iyer

Inventor： Zhen Fang ,  Mahesh Wagh ,  Jasmin Ajanovic ,  Michael E. Espig ,  Ravishankar Iyer

IPC: G06F12/08

CPC classification number: G06F12/1036 ,  G06F12/0292 ,  G06F12/0888 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/206

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract translation: 描述了用于控制片上系统结构（OSF）块的方法和装置。 在一个实施例中，响应于用户级请求可以存储对应于物理地址的影子地址，并且逻辑电路（例如，存在于OSF中）可以从影子地址确定物理地址。 还公开了其他实施例。

公开(公告)号：US20120233393A1

公开(公告)日：2012-09-13

申请号：US13042547

申请日：2011-03-08

Applicant: Xiaowei Jiang ,  Li Zhao ,  Ravishankar Iyer

Inventor： Xiaowei Jiang ,  Li Zhao ,  Ravishankar Iyer

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0842 ,  G06F9/46 ,  G06F9/4881 ,  G06F2209/483

Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.

Abstract translation: 在一个实施例中，处理器包括第一高速缓存和第二高速缓存，与第一高速缓存相关联的第一核和与第二高速缓存相关联的第二核。 高速缓存具有非对称尺寸，并且调度器可以至少部分地基于对至少一个线程的训练阶段期间获得的不对称性和结果高速缓存性能信息的认识来智能地将线程调度到核心。

公开(公告)号：US20120173907A1

公开(公告)日：2012-07-05

申请号：US13341657

申请日：2011-12-30

Applicant: Jaideep MOSES ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Jared E. Bendt ,  Sadagopan Srinivasan ,  Andrew J. Herdrich ,  Ashish V. Choubal ,  Avinash N. Ananthakrishnan ,  Vijay S.R. Degalahal

Inventor： Jaideep MOSES ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Jared E. Bendt ,  Sadagopan Srinivasan ,  Andrew J. Herdrich ,  Ashish V. Choubal ,  Avinash N. Ananthakrishnan ,  Vijay S.R. Degalahal

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/3287 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.

Abstract translation: 描述了用于设备的能量效率操作的系统，装置和方法的实施例。 在一些实施例中，监视高速缓存的高速缓存性能指示符，并且确定基于高速缓存性能指示符的一个或多个高速缓存性能参数的集合。 基于缓存性能参数与其节能目标的比较来缓存高速缓存大小，以达到最佳高速缓存大小，从而降低功耗。

公开(公告)号：US20120079235A1

公开(公告)日：2012-03-29

申请号：US12890653

申请日：2010-09-25

Applicant: Ravishankar Iyer ,  Sadagopan Srinivasan ,  Li Zhao ,  Rameshkumar G. Illikkal

Inventor： Ravishankar Iyer ,  Sadagopan Srinivasan ,  Li Zhao ,  Rameshkumar G. Illikkal

IPC: G06F9/305 ,  G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/5027 ,  G06F11/3409 ,  G06F11/3433 ,  G06F12/084 ,  G06F2201/88 ,  G06N5/02 ,  Y02D10/13 ,  Y02D10/22 ,  Y02D10/34

Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

Abstract translation: 描述了在异构多处理器计算平台中调度应用程序的方法和装置。 在一个实施例中，处理器的多个处理器核的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。 处理器中的逻辑根据存储的信息确定哪个处理器内核应该执行应用程序。 还要求和公开其它实施例。