公开(公告)号：US20070121418A1

公开(公告)日：2007-05-31

申请号：US11560746

申请日：2006-11-16

Applicant: Hyun-Jin KIM ,  Seong-Jin JANG ,  Jeong-Don LIM ,  Kwang-Il PARK ,  Ho-Young SONG ,  Woo-Jin LEE

Inventor： Hyun-Jin KIM ,  Seong-Jin JANG ,  Jeong-Don LIM ,  Kwang-Il PARK ,  Ho-Young SONG ,  Woo-Jin LEE

IPC: G11C8/00

CPC classification number: G06F12/02 ,  G11C7/1078 ,  G11C7/109

Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

Abstract translation: 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US20070121397A1

公开(公告)日：2007-05-31

申请号：US11601027

申请日：2006-11-17

Applicant: Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

Inventor： Woo-Jin Lee ,  Hyun-Dong Kim ,  Seong-Jin Jang

IPC: G11C29/00

CPC classification number: G11C29/48 ,  G11C7/1051 ,  G11C7/1069 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14

Abstract: A semiconductor memory device and a method of expanding a valid output data window are described. The semiconductor memory device includes a memory cell array and an output circuit. The memory cell array generates read data having a plurality of bits. The output circuit outputs the, read data sequentially in response to a clock signal in a normal mode. On the other hand, the output circuit selectively outputs the bits of the read data by latching bits to be tested among bits of the read data, and by electrically disconnecting bits not to be tested among bits of the read data in response to a plurality of switch control signals in a test mode. Therefore a valid data window of an output data may be expanded.

Abstract translation: 描述半导体存储器件和扩展有效输出数据窗口的方法。 半导体存储器件包括存储单元阵列和输出电路。 存储单元阵列产生具有多个位的读取数据。 输出电路响应于正常模式下的时钟信号顺序地输出读取数据。 另一方面，输出电路通过在读取数据的比特之间锁存待测试的比特来选择性地输出读取的数据的比特，并且响应于多个读取数据，通过电连接在读取的数据的比特之间的不被测试的比特 在测试模式下切换控制信号。 因此，可以扩展输出数据的有效数据窗口。

公开(公告)号：US20070069213A1

公开(公告)日：2007-03-29

申请号：US11475668

申请日：2006-06-27

Applicant: Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim

Inventor： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim

IPC: H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L31/112

CPC classification number: G11C7/02 ,  G11C7/1048 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

Abstract: A termination value for a pin of a semiconductor device is set to a first value if a pin signal has a first logic state at an edge of a control signal, and to a second value if the pin signal has a second logic state at the edge of the control signal. Alternatively, a respective logic state of a first control signal is determined at an edge of a second control signal, and a respective logic state of the pin signal is determined at the edge of the second control signal. The termination value is set depending on such respective logic states.

Abstract translation: 如果引脚信号在控制信号的边缘处具有第一逻辑状态，则半导体器件的引脚的终止值被设置为第一值，并且如果引脚信号在边沿处具有第二逻辑状态，则将第二值设置为第二值 的控制信号。 或者，在第二控制信号的边缘确定第一控制信号的相应逻辑状态，并且在第二控制信号的边缘确定引脚信号的相应逻辑状态。 终止值根据这些各自的逻辑状态来设定。

公开(公告)号：US07015739B2

公开(公告)日：2006-03-21

申请号：US10793001

申请日：2004-03-04

Applicant: Woo-Jin Lee ,  Kyu-Hyoun Kim

Inventor： Woo-Jin Lee ,  Kyu-Hyoun Kim

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

Abstract translation: 提供了数字占空比校正电路，其包括占空比检测器电路，其被配置为分别产生与第一内部时钟信号和第二内部时钟信号相关联的第一和第二控制值。 还提供比较器电路，并且被配置为将第一控制值与第二控制值进行比较并提供比较结果。 计数器电路被配置为响应于比较结果执行加法和/或减法操作以提供数字代码。 数模转换器被配置为响应于数字代码产生第三和第四控制值。 最后，占空比校正器电路被配置为接收第一和第二外部时钟信号以及第一至第四控制值，并产生具有校正占空比的第一和第二内部时钟信号。 通过第一路径接收第一和第二控制值，并且通过不同于第一路径的第二路径接收第三和第四控制值。 还提供了操作占空比校正电路的相关方法。

公开(公告)号：US06797624B2

公开(公告)日：2004-09-28

申请号：US10288058

申请日：2002-11-05

Applicant: Woo Jin Lee

Inventor： Woo Jin Lee

IPC: H01L21302

CPC classification number: C23F3/00 ,  H01L21/3212 ,  H01L28/65 ,  Y10S438/959

Abstract: A solution for ruthenium chemical mechanical planarization containing a nitric acid and an oxidizer is disclosed. A method of forming ruthenium pattern using a polished ruthenium layer is also disclosed. The disclosed solution improves the polishing speed of ruthenium under low polishing pressure, reduces the dishing of ruthenium and decreases scratches generated in the interlayer insulating film. As a result, the disclosed solution and methods improve the techniques for device isolation and reduction of step coverage.

Abstract translation: 公开了含有硝酸和氧化剂的钌化学机械平面化的溶液。 还公开了使用抛光的钌层形成钌图案的方法。 所公开的溶液提高了在低抛光压力下钌的抛光速度，减少了钌的凹陷并减少了层间绝缘膜中产生的划痕。 因此，所公开的解决方案和方法改进了用于设备隔离和降低台阶覆盖率的技术。

公开(公告)号：US5714708A

公开(公告)日：1998-02-03

申请号：US720024

申请日：1996-09-27

Applicant: Woo-Jeon Shim ,  Il-Soo Kim ,  Kil-Ho Hong ,  Woo-Jin Lee

Inventor： Woo-Jeon Shim ,  Il-Soo Kim ,  Kil-Ho Hong ,  Woo-Jin Lee

IPC: F41F3/052 ,  F41F3/00

CPC classification number: F41F3/052

Abstract: An improved missile restraining apparatus capable of effectively protecting a missile from an external impact and quickly releasing a missile restraining state when launching missile, which includes a pair of protrusions having a circular cross-section and formed in the rear portion of a missile, and a pair of brackets fixed to the inner surface of a launch tube and formed so that a pair of restraining grooves corresponding to said protrusions are formed in a predetermined direction, wherein one end of said restraining groove has a circular cross-section, and the other end thereof is shaped to have an elongating axis longer than the diameter of the protrusion in the radial direction and to have the same shorter axis as the restraining groove in the vertical direction.

Abstract translation: 一种改进的导弹限制装置，能够有效地保护导弹免受外部冲击，并且在发射导弹时迅速释放导弹限制状态，导弹包括一对具有圆形横截面并形成在导弹后部的突起，以及 一对支架固定在发射管的内表面上并且形成为使得一对对应于所述突起的约束槽沿预定方向形成，其中所述限制槽的一端具有圆形横截面，另一端 成形为具有比突起在径向方向上的直径长的延伸轴线，并且在垂直方向上具有与限制槽相同的短轴。

公开(公告)号：US20160163589A1

公开(公告)日：2016-06-09

申请号：US14955988

申请日：2015-12-01

Applicant: Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

Inventor： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047

Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Abstract translation: 形成半导体器件的方法可以包括使用具有选择为提供对后续蚀刻工艺的电阻的组成的材料形成绝缘层。 可以改变材料的组成以将材料的电阻降低到绝缘层中预定水平的后续蚀刻工艺。 可以在绝缘层上执行随后的蚀刻工艺，以将绝缘层的上部去除在预定水平以上，并且将绝缘层的下部分留在延伸穿过绝缘层的下部的相邻导电图案之间的预定水平以下 。 可以在相邻导电图案之间的绝缘层的下部上形成低k介电材料，以将绝缘层的上部替换为高于预定水平。

公开(公告)号：US20160079115A1

公开(公告)日：2016-03-17

申请号：US14703556

申请日：2015-05-04

Applicant: Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

Inventor： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76843 ,  H01L2221/1063

Abstract: A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

Abstract translation: 一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成 包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案， 衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

公开(公告)号：US08917250B2

公开(公告)日：2014-12-23

申请号：US13312138

申请日：2011-12-06

Applicant: Jae Hun Kim ,  Sang Su Hong ,  Chung Mo Yang ,  In Hyung Lee ,  Woo Jin Lee ,  Young Woo Lee

Inventor： Jae Hun Kim ,  Sang Su Hong ,  Chung Mo Yang ,  In Hyung Lee ,  Woo Jin Lee ,  Young Woo Lee

IPC: G06F3/041 ,  H05K1/02

CPC classification number: G06F3/041 ,  G06F2203/04103 ,  H05K1/0289 ,  H05K2201/0108 ,  H05K2201/056

Abstract: Disclosed herein is a structure of an FPC integrated touch panel. According to preferred embodiments of the present invention, a transparent substrate configured of a flexible transparent film is provided and an extension part protruded to the transparent substrate is integrally formed with the transparent substrate, such that a separate FPC needs not to be manufactured, thereby saving process time and manufacturing costs. In addition, the exemplary embodiments of the present invention bend an inactive area unnecessarily occupying an area of the transparent substrate to a side of the touch panel, thereby implementing a touch panel widening a substantial area of an active region.

Abstract translation: 这里公开了FPC集成触摸面板的结构。 根据本发明的优选实施例，提供由柔性透明膜构成的透明基板，并且向透明基板突出的延伸部分与透明基板一体形成，使得不需要制造单独的FPC，从而节省 处理时间和制造成本。 此外，本发明的示例性实施例将不需要地占据透明基板的区域的非活性区域弯曲到触摸面板的一侧，从而实现扩大有源区域的实质区域的触摸面板。

公开(公告)号：US08669185B2

公开(公告)日：2014-03-11

申请号：US12847848

申请日：2010-07-30

Applicant: Shigeyuki Onizawa ,  Woo-Jin Lee ,  Hideaki Fukuda ,  Kunitoshi Namba

Inventor： Shigeyuki Onizawa ,  Woo-Jin Lee ,  Hideaki Fukuda ,  Kunitoshi Namba

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/31 ,  C23C16/00

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/0228

Abstract: A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.

Abstract translation: 定制沉积在图案化表面上的膜的共形性的方法包括：（I）通过PEALD或脉冲PECVD在图案化表面上沉积膜; （II）蚀刻所述膜，其中所述蚀刻以脉冲或脉冲进行，其中所述图案的所述膜上的所述膜的蚀刻速率与所述图案的侧壁上的膜的蚀刻速率的比率被控制为 蚀刻脉冲持续时间和蚀刻脉冲数以增加膜的共形度; 和（III）重复（I）和（II）以满足目标膜厚度。