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公开(公告)号：US11755804B2
公开(公告)日：2023-09-12
申请号：US17646184
申请日：2021-12-28
Applicant: Xilinx, Inc.
Inventor： Albert Shih-Huai Lin , Rambabu Nerukonda , Niravkumar Patel , Amitava Majumdar
IPC: G06F30/333 , G06F30/367 , G06F30/396 , G06F30/398 , G06F30/20 , G06F11/267 , G06F11/27 , H01L25/00 , H03K19/17732 , H03K19/17764 , G06F115/08 , H01L21/66
CPC classification number: G06F30/333 , H03K19/17732 , H03K19/17764 , G06F11/267 , G06F11/27 , G06F30/20 , G06F30/367 , G06F30/396 , G06F30/398 , G06F2115/08 , H01L22/34 , H01L25/00
Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.
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公开(公告)号：US11743134B2
公开(公告)日：2023-08-29
申请号：US17065438
申请日：2020-10-07
Applicant: XILINX, INC.
Inventor： Guanwen Zhong , Chengchen Hu , Gordon John Brebner
CPC classification number: H04L41/20 , H04L43/04 , H04L47/22 , H04L47/215 , H04L47/623
Abstract: Examples herein describe a programmable traffic management engine that includes both programmable and non-programmable hardware components. The non-programmable hardware components are used to generate features that can then be used to perform different traffic management algorithms. Depending on which traffic management algorithm the PTM engine is configured to do, the PTM engine may use a subset (or all) of the features to perform the algorithm. The programmable hardware components in the PTM engine are programmable (e.g., customizable) by the user to perform a selected algorithm using some or all of the features provided by the non-programmable hardware components.
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公开(公告)号：US11743051B2
公开(公告)日：2023-08-29
申请号：US17083195
申请日：2020-10-28
Applicant: XILINX, INC.
Inventor： Haris Javaid , Ji Yang , Sundararajarao Mohan , Gordon John Brebner
IPC: H04L9/32 , G06F16/23 , G06F30/331 , H04L9/00
CPC classification number: H04L9/3247 , G06F16/2336 , G06F30/331 , H04L9/321 , H04L9/50 , H04L2209/125
Abstract: Embodiments herein describe a hardware accelerator for a blockchain node. The hardware accelerator is used to perform a validation operation to validate one or more transactions before those transactions are committed to a ledger of a blockchain. The blockchain may include multiple peer-nodes, each of which contains standard software running on a server or container. Instead of validating a block of transactions using software, the hardware accelerator can validate the transactions in a fraction of the time. The peer-node software then gathers the validation results from the hardware accelerator and combines the results with received block data to derive the block which is committed to the stored ledger.
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公开(公告)号：US11730325B2
公开(公告)日：2023-08-22
申请号：US17468346
申请日：2021-09-07
Applicant: XILINX, INC.
Inventor： Peter McColgan , Goran Hk Bilski , Juan J. Noguera Serra , Jan Langer , Baris Ozgul , David Clarke
CPC classification number: A47K11/02 , E04H1/1216 , E04H15/38 , G06F13/4022 , Y02A50/30
Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.
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公开(公告)号：US20230259627A1
公开(公告)日：2023-08-17
申请号：US17651030
申请日：2022-02-14
Applicant: Xilinx, Inc.
Inventor： Sonal Santan , Yu Liu , Yenpang Lin , Lizhi Hou , Cheng Zhen , Yidong Zhang
CPC classification number: G06F21/572 , G06F21/64 , G06F21/71 , G06F13/1642 , G06F13/1663
Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.
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Patent Agency Ranking
公开(公告)号：US11721651B2
公开(公告)日：2023-08-08
申请号：US17037363
申请日：2020-09-29
Applicant: XILINX, INC.
Inventor： Chi Fung Poon , Asma Laraba , Parag Upadhyaya
IPC: H01L23/66 , H01L23/538 , H01L25/16
CPC classification number: H01L23/66 , H01L23/5386 , H01L25/16 , H01L2224/02379
Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.
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公开(公告)号：US11720422B1
公开(公告)日：2023-08-08
申请号：US17198887
申请日：2021-03-11
Applicant: Xilinx, Inc.
Inventor： Hem C. Neema , Sonal Santan , Soren T. Soe , Stephen P. Rozum , Nik Cimino
CPC classification number: G06F9/545 , G06F8/44 , G06F21/53 , G06F21/572 , G06F8/65
Abstract: A unified container file can be selected using computer hardware. The unified container file can include a plurality of files embedded therein used to configure a programmable integrated circuit (IC). The plurality of files can include a first partial configuration bitstream and a second partial configuration bitstream. The unified container file also includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable IC. The defined relationship can be determined using computer hardware by reading the metadata from the unified container file. The programmable IC can be configured, using the computer hardware, based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream.
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公开(公告)号：US20230244966A1
公开(公告)日：2023-08-03
申请号：US17649912
申请日：2022-02-03
Applicant: Xilinx, Inc.
Inventor： Varun Sharma , Aaron Ng
Abstract: An inference server is capable of receiving a plurality of inference requests from one or more client systems. Each inference request specifies one of a plurality of different endpoints. The inference server can generate a plurality of batches each including one or more of the plurality of inference requests directed to a same endpoint. The inference server also can process the plurality of batches using a plurality of workers executing in an execution layer therein. Each batch is processed by a worker of the plurality of workers indicated by the endpoint of the batch.
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公开(公告)号：US11716089B1
公开(公告)日：2023-08-01
申请号：US17696734
申请日：2022-03-16
Applicant: XILINX, INC.
Inventor： Bob W. Verbruggen , Christophe Erdmann
IPC: H03M1/06
CPC classification number: H03M1/0604 , H03M1/0682
Abstract: A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.
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公开(公告)号：US20230240020A1
公开(公告)日：2023-07-27
申请号：US17586212
申请日：2022-01-27
Applicant: XILINX, INC.
Inventor： Bhavesh PATEL
CPC classification number: H05K3/3436 , H05K1/115 , H05K1/024 , H05K2201/10734 , H05K2201/0183
Abstract: An electronic device and methods for fabricating the same are disclosed herein that utilize a dam formed on a printed circuit board (PCB) that is positioned to substantially prevent edge bond material, utilized to secure a chip package to the PCB, from interfacing with the solder balls transmitting signals between the PCB and chip package.
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