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342 条记录 (耗时 0.034 秒)

    System and method for decoding commands based on command signals and operating state
    84.
    发明申请
    System and method for decoding commands based on command signals and operating state 有权
    基于命令信号和操作状态对命令进行解码的系统和方法

    公开(公告)号：US20060265556A1

    公开(公告)日：2006-11-23

    申请号：US11121868

    申请日：2005-05-03

    申请人： Jeffery Janzen ,  Brent Keeth ,  Jeffrey Wright ,  James Cullum

    发明人： Jeffery Janzen ,  Brent Keeth ,  Jeffrey Wright ,  James Cullum

    IPC分类号： G06F13/00

    CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

    摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

    On-chip sampling circuit and method
    85.
    发明申请
    On-chip sampling circuit and method 有权
    片上采样电路及方法

    公开(公告)号：US20060236170A1

    公开(公告)日：2006-10-19

    申请号：US11109535

    申请日：2005-04-19

    申请人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

    发明人： Chris Martin ,  James Johnson ,  Troy Manning ,  Brent Keeth

    IPC分类号： G01R31/28

    CPC分类号： G11C29/48 ,  G11C29/1201

    摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

    摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。 由于与摘要相关的规则，本摘要不应用于索赔的构建。

    Memory system and method for strobing data, command and address signals
    86.
    发明申请
    Memory system and method for strobing data, command and address signals 有权

    公开(公告)号：US20060126406A1

    公开(公告)日：2006-06-15

    申请号：US11352142

    申请日：2006-02-10

    申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

    摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

    Semiconductor memory circuitry
    87.
    发明授权
    Semiconductor memory circuitry 失效
    半导体存储器电路

    公开(公告)号：US07057225B2

    公开(公告)日：2006-06-06

    申请号：US10304804

    申请日：2002-11-26

    申请人： Brent Keeth ,  Pierre C Fazan

    发明人： Brent Keeth ,  Pierre C Fazan

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/105 ,  H01L27/108 ,  H01L27/10811 ,  Y10T29/49121

    摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells. The memory cells are formed with a minimum capable photolithographic feature dimension. A single memory cell consumes an area of no more than eight times the square of the minimum capable photolithographic feature dimension.

    摘要翻译： 公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。 集成电路包括半导体管芯，布置在形成在半导体管芯上的至少一个阵列中的多个功能和可操作地寻址的存储器单元，以及形成在半导体管芯上并耦合到存储器单元的电路，用于允许数据被写入到 从内存单元读取。 存储单元由最小能力的光刻特征尺寸形成。 单个存储器单元消耗的面积不超过最小能力光刻特征尺寸的平方的八倍。

    Method and apparatus for data compression in memory devices
    88.
    发明授权
    Method and apparatus for data compression in memory devices 失效

    公开(公告)号：US06987702B2

    公开(公告)日：2006-01-17

    申请号：US10879935

    申请日：2004-06-28

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： G11C11/00

    CPC分类号： G11C29/1201 ,  G11C29/40

    摘要： A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays. Combinatorial logic then determines if both of the data lines have the same logical value, indicating disagreement between the data from the memory arrays that may indicate the presence of a defective memory cell in one or the other array. Thus, in the test mode, data are simultaneously coupled to the inputs of the DC sense amplifier from respective digit lines coupled to two different memory cells, thereby increasing the rate at which background data that has been written to the arrays can be read from the arrays.

    Method and apparatus for data compression in memory devices
    89.
    发明申请
    Method and apparatus for data compression in memory devices 有权

    公开(公告)号：US20050286326A1

    公开(公告)日：2005-12-29

    申请号：US11218038

    申请日：2005-08-31

    申请人： Brent Keeth

    发明人： Brent Keeth

    IPC分类号： G11C29/00 ,  G11C29/40

    CPC分类号： G11C29/1201 ,  G11C29/40

    摘要： A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of complementary digit lines is provided for each column of each array. The digit lines are selectively coupled to a pair of I/O lines for each array which are, in turn, coupled to a pair of complementary data lines. The data lines are coupled to respective inputs of a DC sense amplifier, one of which is provided for each array. A multiplexer connects the pair of I/O lines for either one of the arrays to the data lines in a normal operating mode. Thus, in the normal operating mode, data are selectively coupled to the inputs of the DC sense amplifier from the complementary digit lines for an addressed column. In a test mode, the multiplexer connects the I/O lines for both arrays to the data lines to compress the data from the two arrays. Combinatorial logic then determines if both of the data lines have the same logical value, indicating disagreement between the data from the memory arrays that may indicate the presence of a defective memory cell in one or the other array. Thus, in the test mode, data are simultaneously coupled to the inputs of the DC sense amplifier from respective digit lines coupled to two different memory cells, thereby increasing the rate at which background data that has been written to the arrays can be read from the arrays.