公开(公告)号：US20070210371A1

公开(公告)日：2007-09-13

申请号：US11653832

申请日：2007-01-17

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

摘要翻译： 存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。 存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。 在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。 形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

公开(公告)号：US20070183206A1

公开(公告)日：2007-08-09

申请号：US11727592

申请日：2007-03-27

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20050208716A1

公开(公告)日：2005-09-22

申请号：US11130236

申请日：2005-05-17

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/49

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/4941 ,  H01L29/6656

摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。 存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。 通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。 此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。 结果，可以以自对准的方式降低硼渗透并形成接触电极。 此外，可以提高构成逻辑电路的MISFET的性能。

公开(公告)号：US20050045933A1

公开(公告)日：2005-03-03

申请号：US10914223

申请日：2004-08-10

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线， 选择线。 由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触， 外围电路区域和存储单元区域之间的台阶高度显着降低。

公开(公告)号：US06831316B1

公开(公告)日：2004-12-14

申请号：US10009826

申请日：2002-03-19

申请人： Hideyuki Matsuoka ,  Takeshi Sakata ,  Shinichiro Kimura ,  Toshiaki Yamanaka ,  Tsuyoshi Kachi ,  Tomonori Sekiguchi

发明人： Hideyuki Matsuoka ,  Takeshi Sakata ,  Shinichiro Kimura ,  Toshiaki Yamanaka ,  Tsuyoshi Kachi ,  Tomonori Sekiguchi

IPC分类号： H01L4700

CPC分类号： H01L27/108 ,  H01L27/10894 ,  H01L27/10897

摘要： An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.

摘要翻译： 存在的DRAM存储单元包括作为开关的晶体管和用于累积存储电荷的电容器，其中电容器的高度随着微型化而逐渐增加，这直接导致制造成本的增加。 本申请的发明提供了一种基本结构的半导体存储器件，其中具有设置在半导体衬底上的多个存储单元的存储单元阵列和用于选择存储单元的字线和数据线以及外围电路的外围电路 存储单元阵列，其中存储单元包括导电层的多层，绝缘层和含有杂质的多个半导体层，并且可以将电位施加到能够实现隧道效应的绝缘层。 本申请的发明涉及不需要电容器并能够以简单的步骤形成的存储单元。

公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06535435B2

公开(公告)日：2003-03-18

申请号：US10012522

申请日：2001-12-12

申请人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

发明人： Hitoshi Tanaka ,  Masakazu Aoki ,  Shinichiro Kimura ,  Hiromasa Noda ,  Tomonori Sekiguchi

IPC分类号： G11C700

CPC分类号： H01L27/0222 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  H01L27/10897

摘要： A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.

摘要翻译： 提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。 推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。 即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。 它还允许在电源打开时快速启动并提供高稳定性。

公开(公告)号：US06376304B1

公开(公告)日：2002-04-23

申请号：US09608154

申请日：2000-06-30

申请人： Hideyuki Matsuoka ,  Shinichiro Kimura ,  Toshiaki Yamanaka

发明人： Hideyuki Matsuoka ,  Shinichiro Kimura ,  Toshiaki Yamanaka

IPC分类号： H01L218242

CPC分类号： H01L27/10882 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.

摘要翻译： 提供一种半导体存储器件及其制造方法，其中在外围电路区域之上形成仅覆盖存储单元阵列外的外围电路区域的层间膜，以减少在形成位线之后的两个区域之间的拓扑差异 ; 因此，以普通表面为主要的半导体衬底可以用作起始体，而不需要预处理，也可以应用浅沟槽隔离技术。 此外，与外围电路的互连可以通过多级插头连接引导到设备的表面，从而处理大的纵横比孔，用金属填充孔等是不必要的，因为 结果，改进了该过程的可靠性。

公开(公告)号：US6157055A

公开(公告)日：2000-12-05

申请号：US185633

申请日：1998-11-04

申请人： Ken Yamaguchi ,  Shinichiro Kimura ,  Masatada Horiuchi ,  Tatsuya Teshima

发明人： Ken Yamaguchi ,  Shinichiro Kimura ,  Masatada Horiuchi ,  Tatsuya Teshima

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10808 ,  H01L27/10873

摘要： In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

摘要翻译： 在诸如DRAM的半导体存储器件中，在隔离绝缘膜（1.2）的与半导体衬底（1.1）相对的边缘部分上布置导电膜（1.11'），其间具有薄的绝缘膜。 该导电膜（1.11'）电连接到存储电容器的下电极（1.11）。 这种新颖的布置可以独立于冶金pn结的位置来控制电pn结的位置，从而实现了抑制泄漏电流增加的数据保持时间长的半导体存储器件。

公开(公告)号：US4970564A

公开(公告)日：1990-11-13

申请号：US287881

申请日：1988-12-21

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10808

摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量 部分布置得非常密集和足够大的容量保持非常小的单元格区域。 此外，在半导体存储器件中，即使在位线上形成存储容量部分。 因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。