公开(公告)号：US08731098B2

公开(公告)日：2014-05-20

申请号：US12882739

申请日：2010-09-15

Applicant: Delong Cui ,  Afshin Momtaz ,  Jun Cao

Inventor： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC: H04L27/04 ,  H04L27/20

CPC classification number: H04L7/0091 ,  H04L7/0008

Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.

Abstract translation: 发射系统包括时钟系统和数据系统。 时钟系统被配​​置为接收具有第一值的时钟并且产生具有第二不同值的控制信号和具有第一值的输出时钟。 数据系统被配置为基于控制信号接收数据和控制信号并使数据与输出时钟对准，以产生输出数据。 时钟系统包括配置成产生输出时钟的驱动器，被配置为对接收的时钟进行分频的分频器，以及被配置为旋转分频时钟以产生控制信号的相位内插器。 此外，数据是并行数据，并且数据系统包括被配置为接收并行数据并且使用控制信号将并行数据串行化为对准数据的多路复用器和被配置为产生输出数据的驱动器。

公开(公告)号：US08618964B2

公开(公告)日：2013-12-31

申请号：US13207887

申请日：2011-08-11

Applicant: Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

Inventor： Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

IPC: H03M1/06

CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.

Abstract translation: 根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。

公开(公告)号：US08618835B2

公开(公告)日：2013-12-31

申请号：US13242643

申请日：2011-09-23

Applicant: Burak Catli ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Ullas Singh ,  Jun Cao ,  Afshin Momtaz

Inventor： Burak Catli ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Ullas Singh ,  Jun Cao ,  Afshin Momtaz

IPC: H03K19/0175

CPC classification number: H03K19/0013 ,  H03K19/018521

Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

Abstract translation: 公开了用于将来自一个数字集成电路系列的信号转换为与另一数字集成电路系列兼容的装置。 该装置包括主接口和辅助接口，用于转换来自一个数字集成电路系列的差分输出信号，以用作另一数字集成电路系列的输入信号。 主接口和辅助接口包括可配置为提供轨至轨电压摆幅的增益级，并且其特征在于具有单极架构。 次级接口可以是未端接的，使得对差分输出信号的两个分量提供基本上相等的负载。

公开(公告)号：US08451058B2

公开(公告)日：2013-05-28

申请号：US13166592

申请日：2011-06-22

Applicant: Delong Cui ,  Afshin Momtaz ,  Jun Cao

Inventor： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC: H03F3/16 ,  H03F3/04

CPC classification number: H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

公开(公告)号：US20120313715A1

公开(公告)日：2012-12-13

申请号：US13158121

申请日：2011-06-10

Applicant: Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Mehdi Khanpour ,  Afshin Momtaz

Inventor： Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Mehdi Khanpour ,  Afshin Momtaz

IPC: H03L7/00 ,  G01R23/02

CPC classification number: G01R23/02 ,  G01R23/15 ,  G01R25/00 ,  H03D13/00 ,  H03L7/00 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/113 ,  H03L2207/06

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract translation: 实施例提供了一种克服常规电路的死区问题的无参考频率检测器。 特别地，频率检测器能够精确地解决VCO时钟信号和数据信号之间的频率差的极性，而不管频率差的大小和数据信号上是否存在VCO时钟抖动和/或ISI 。

公开(公告)号：US20120169428A1

公开(公告)日：2012-07-05

申请号：US13094802

申请日：2011-04-26

Applicant: Hassan Maarefi ,  Afshin Momtaz

Inventor： Hassan Maarefi ,  Afshin Momtaz

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B5/1296

Abstract: A voltage controlled oscillator (VCO) may include a stack of a plurality of non-connected inductors that are magnetically and/or electrically through capacitor (AC) coupled to each other and not directly physically connected to each other. The plurality of inductors includes a first inductor connected to a supply voltage and a second inductor connected to a VCO control voltage. The VCO may include a first varactor having a gate coupled to a first terminal of the second inductor to receive the VCO control voltage, a second varactor having a gate coupled to a second terminal of the second inductor to receive the VCO control voltage, and an oscillator sub-circuit coupled to first and second terminals of the first inductor. In one example implementation, the second inductor may contribute to the overall inductance of the inductor stack and provide AC decoupling and/or DC coupling between the VCO control voltage and the varactor(s).

Abstract translation: 压控振荡器（VCO）可以包括多个非连接电感器的堆叠，其通过彼此耦合并且不直接物理地彼此连接的电容器（AC）磁性和/或电气电连接。 多个电感器包括连接到电源电压的第一电感器和连接到VCO控制电压的第二电感器。 VCO可以包括具有耦合到第二电感器的第一端子的栅极以接收VCO控制电压的第一变容二极管，具有耦合到第二电感器的第二端子以接收VCO控制电压的栅极的第二变容二极管，以及 振荡器子电路耦合到第一电感器的第一和第二端子。 在一个示例实施例中，第二电感器可以有助于电感器堆叠的整体电感，并且在VCO控制电压和变容二极管之间提供AC去耦和/或DC耦合。

公开(公告)号：US20120027074A1

公开(公告)日：2012-02-02

申请号：US12878689

申请日：2010-09-09

Applicant: Bharath RAGHAVAN ,  Afshin Momtaz ,  Jun Cao

Inventor： Bharath RAGHAVAN ,  Afshin Momtaz ,  Jun Cao

IPC: H04L27/01

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/061 ,  H04L25/10 ,  H04L2025/03356 ,  H04L2025/03382 ,  H04L2025/03503

Abstract: Embodiments of a summer block for a Decision Feedback Equalizer are provided herein. The summer block is configured to offset a combination of a Feed Forward Equalized (FFE) data signal and a Feedback Equalized (FBE) data signal by a dc amount. The dc amount is based on at least a weight of a tap previously implemented with an FBE of the DFE. The summer block can be further configured to offset the combination of the FFE data signal and the FBE data signal based on a dc offset value necessary to compensate for asymmetries in the data eye of data received by the FFE over a channel and a dc offset value necessary to compensate for mismatches present in the circuits of the DFE.

Abstract translation: 本文提供了用于判决反馈均衡器的加法块的实施例。 加法块被配置为通过直流量偏移前馈均衡（FFE）数据信号和反馈均衡（FBE）数据信号的组合。 直流量基于以前用DFE的FBE实现的抽头的重量。 加法块可以进一步配置为基于补偿由FFE在信道上接收的数据的数据眼中的不对称所必需的直流偏移值和直流偏移值来补偿FFE数据信号和FBE数据信号的组合 必须补偿DFE电路中存在的不匹配。

公开(公告)号：US08077819B2

公开(公告)日：2011-12-13

申请号：US12571994

申请日：2009-10-01

Applicant: Afshin Momtaz ,  Rajesh Satapathy ,  Chung-Jue Chen

Inventor： Afshin Momtaz ,  Rajesh Satapathy ,  Chung-Jue Chen

IPC: H04B1/10

CPC classification number: H04L25/03057 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L2025/0349 ,  H04L2025/03617 ,  H04L2025/03662 ,  H04L2025/03687 ,  H04L2025/037

Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.

Abstract translation: 搜索引擎选择接收均衡器的初始系数。 搜索引擎可以并入到包括判决反馈均衡器和时钟和数据恢复电路的通信接收器中。 这里，搜索引擎可以初始化可以控制例如判决反馈均衡器，时钟和数据恢复电路以及连续时间滤波器的操作的各种适配环路。 接收机可以包括用于产生一些适配环路的软判决数据的模拟 - 数字转换器。

公开(公告)号：US07956645B2

公开(公告)日：2011-06-07

申请号：US12049701

申请日：2008-03-17

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03K19/094

CPC classification number: H03K19/017509

Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

Abstract translation: 低功耗高速输出驱动。 一组开关（其中一些是反向开关，其连接性与提供给它的控制信号相反地控制），使得输入信号控制这些开关的连接。 电阻器耦合在插入阵列的开关之间的节点之间，并且从电阻器端部处的节点获取输出信号。 这种输出驱动器的高电压电平实际上是在仍然消耗相对较低的功率的情况下为电路供电（例如，VDD）的电源的电平。

公开(公告)号：US20110074610A1

公开(公告)日：2011-03-31

申请号：US12567841

申请日：2009-09-28

Applicant: Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

Inventor： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

IPC: H03M7/12

CPC classification number: H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

Abstract translation: 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 该电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。