公开(公告)号：US10685881B2

公开(公告)日：2020-06-16

申请号：US16112511

申请日：2018-08-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Haiting Wang

IPC: H01L21/70 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/66

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.

公开(公告)号：US10685840B2

公开(公告)日：2020-06-16

申请号：US16193960

申请日：2018-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.

公开(公告)号：US20200176258A1

公开(公告)日：2020-06-04

申请号：US16203816

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  David P. Brunco

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.

公开(公告)号：US20200168509A1

公开(公告)日：2020-05-28

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US20200161190A1

公开(公告)日：2020-05-21

申请号：US16196413

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/762

Abstract: One illustrative IC product disclosed herein includes an isolation structure that separates a fin into a first fin portion and a second fin portion, an epi semiconductor material positioned on the first fin portion in a source/drain region of a transistor device, wherein a lateral gap is present between a first sidewall of the epi semiconductor material and a second sidewall of the SDB isolation structure, and a conductive source/drain structure that is conductively coupled to the epi semiconductor material, wherein a gap portion of the conductive source/drain structure is positioned in the gap and physically contacts the first sidewall and the second sidewall.

公开(公告)号：US20200152518A1

公开(公告)日：2020-05-14

申请号：US16185675

申请日：2018-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/40

Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

公开(公告)号：US20200135723A1

公开(公告)日：2020-04-30

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

公开(公告)号：US20200127109A1

公开(公告)日：2020-04-23

申请号：US16164867

申请日：2018-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Guowei Xu ,  Hui Zang

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.

公开(公告)号：US10600914B2

公开(公告)日：2020-03-24

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L27/11 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US10566202B1

公开(公告)日：2020-02-18

申请号：US16203623

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Hong Yu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423

Abstract: A method of fabricating a semiconductor device is provided, including providing sacrificial gate structures over a plurality of fins. The sacrificial gate structures include a sacrificial first gate structure and a sacrificial second gate structure. A first gate cut process is performed to form a first gate cut opening in the sacrificial first gate structure, and a second gate cut opening in the sacrificial second gate structure. A first dielectric layer is deposited in the first gate cut opening and the second gate cut opening. The first dielectric layer completely fills the first gate cut opening and partially fills the second gate cut opening. The first dielectric layer is removed from the second gate cut opening, and a second gate cut process is performed. A second dielectric layer is deposited in the second gate cut opening to form a gate cut structure.