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    MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE
    83.
    发明申请
    MULTIPLE FIN FINFET WITH LOW-RESISTANCE GATE STRUCTURE 审中-公开
    具有低电阻门结构的多个FIN FINFET

    公开(公告)号：US20150311199A1

    公开(公告)日：2015-10-29

    申请号：US14264240

    申请日：2014-04-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

    IPC: H01L27/088 ,  H01L23/532 ,  H01L23/528 ,  H01L29/16 ,  H01L29/161

    CPC classification number: H01L29/161 ,  H01L23/4824 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

    Abstract translation: 本发明的实施例提供具有低电阻栅极结构的多鳍场效应晶体管（finFET）。 金属化线与栅极平行地形成，并且多个触点形成在将金属化线连接到栅极的鳍上。 金属化线提供降低的栅极电阻，这允许更少的晶体管用于提供输入输出（IO）功能，从而提供节省空间以实现电路密度的增加。

    METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS
    85.
    发明申请
    METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS 有权
    同时形成局部接触开口的FINFET集成电路的制作方法

    公开(公告)号：US20150214113A1

    公开(公告)日：2015-07-30

    申请号：US14164582

    申请日：2014-01-27

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

    IPC: H01L21/8234 ,  H01L29/16 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49

    CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

    Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

    Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

    Semiconductor device and method
    86.
    发明授权
    Semiconductor device and method 有权

    公开(公告)号：US10833161B2

    公开(公告)日：2020-11-10

    申请号：US16253321

    申请日：2019-01-22

    Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

    Inventor： Syed Muhammad Yasser Sherazi ,  Julien Ryckaert ,  Juergen Boemmels ,  Guillaume Bouche

    IPC: H01L29/417 ,  H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66

    Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

    Self aligned buried power rail
    88.
    发明授权
    Self aligned buried power rail 有权

    公开(公告)号：US10475692B2

    公开(公告)日：2019-11-12

    申请号：US15481826

    申请日：2017-04-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nicholas V. Licausi ,  Guillaume Bouche ,  Lars W. Liebmann

    IPC: H01L21/74 ,  H01L27/108 ,  H01L27/088 ,  H01L27/092 ,  H01L23/528 ,  H01L23/535

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

    Self-aligned gate cut isolation
    89.
    发明授权
    Self-aligned gate cut isolation 有权

    公开(公告)号：US10366930B1

    公开(公告)日：2019-07-30

    申请号：US16005064

    申请日：2018-06-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Kangguo Cheng ,  Guillaume Bouche

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

    Abstract: A method includes forming a plurality of fins above a substrate. A first placeholder gate electrode is formed above the plurality of fins. The first placeholder gate electrode includes a placeholder material. A first sacrificial gate cut structure of a sacrificial material different than the placeholder material embedded in the first placeholder gate electrode is formed. A portion of the first placeholder gate electrode positioned above the first sacrificial gate cut structure is removed, exposing the first sacrificial gate cut structure. The first sacrificial gate cut structure is removed to define a gate cut cavity extending vertically through the first placeholder gate electrode. A dielectric material is formed in the gate cut cavity to define a gate cut structure. The first placeholder gate electrode is removed to define a first gate cavity segmented by the gate cut structure. A first replacement gate structure is formed in the first gate cavity.

    METHODS OF PATTERNING DIELECTRIC LAYERS FOR METALLIZATION AND RELATED STRUCTURES
    90.
    发明申请
    METHODS OF PATTERNING DIELECTRIC LAYERS FOR METALLIZATION AND RELATED STRUCTURES 审中-公开

    公开(公告)号：US20190206795A1

    公开(公告)日：2019-07-04

    申请号：US15860193

    申请日：2018-01-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Guillaume Bouche

    IPC: H01L23/538 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5386

    Abstract: Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.

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