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    SEMICONDUCTOR DEVICE WITH LOW-K SPACERS
    84.
    发明申请
    SEMICONDUCTOR DEVICE WITH LOW-K SPACERS 有权
    具有低K间隔的半导体器件

    公开(公告)号：US20150255561A1

    公开(公告)日：2015-09-10

    申请号：US14711196

    申请日：2015-05-13

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Xunyuan Zhang

    IPC分类号： H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

    摘要： One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

    摘要翻译： 本文公开的一种方法包括形成邻近牺牲栅极结构的至少一个牺牲侧壁间隔物，所述牺牲栅极结构形成在半导体衬底上方，去除牺牲栅极结构的至少一部分，从而限定由牺牲隔离物横向限定的栅极腔， 在栅极腔中形成替代栅极结构，去除牺牲隔离物，从而限定邻近置换栅极结构的间隔空腔，并在间隔空腔中形成低k隔离物。 本文公开的新型器件包括位于半导体衬底上方的栅极结构，其中栅绝缘层具有相对于衬底的上表面基本上垂直取向的两个直立部分。 该装置还包括邻近栅极绝缘层的垂直取向的竖立部分的低k侧壁间隔件。

    CAP LAYERS FOR SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS
    85.
    发明申请
    CAP LAYERS FOR SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS 审中-公开
    具有自对准接触元件的半导体器件的CAP层

    公开(公告)号：US20150243604A1

    公开(公告)日：2015-08-27

    申请号：US14711280

    申请日：2015-05-13

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Xiuyu Cai ,  Larry Zhao

    IPC分类号： H01L23/532 ,  H01L23/535 ,  H01L29/78

    CPC分类号： H01L23/53295 ,  H01L23/535 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

    摘要翻译： 本文公开的一种方法包括在凹陷的侧壁间隔物和凹入的替换栅极结构上方形成蚀刻停止层，并且将蚀刻停止层置于适当位置，形成在形成自身之后与源/漏区导电耦合的自对准接触 联系人。 本文公开的装置包括位于凹入的替代栅极结构和凹陷的侧壁间隔物之上的蚀刻停止层，其中蚀刻停止层限定了包含定位在其中的绝缘材料层的蚀刻停止凹部。 该装置还包括自对准接触件。

    Method and device for self-aligned contact on a non-recessed metal gate
    86.
    发明授权
    Method and device for self-aligned contact on a non-recessed metal gate 有权
    在非凹槽金属门上进行自对准接触的方法和装置

    公开(公告)号：US09076816B2

    公开(公告)日：2015-07-07

    申请号：US14080842

    申请日：2013-11-15

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/49

    CPC分类号： H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/6653 ,  H01L29/78

    摘要： A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.

    摘要翻译： 公开了一种用于形成展现出接触到栅极短路故障的可能性降低的自对准接触（SAC）的方法以及所得到的器件。 实施例可以包括在衬底上形成具有相对侧面的间隔物的替换金属栅极，在替代金属栅极的外边缘上在间隔物的上表面中形成凹部，并在该金属栅极上形成氮化铝（AlN） 金属门和凹槽。

    Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices
    87.
    发明授权
    Methods of forming cap layers for semiconductor devices with self-aligned contact elements and the resulting devices 有权
    形成具有自对准接触元件的半导体器件的盖层以及所得到的器件的方法

    公开(公告)号：US09070711B2

    公开(公告)日：2015-06-30

    申请号：US13957991

    申请日：2013-08-02

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ruilong Xie ,  Xiuyu Cai ,  Larry Zhao

    IPC分类号： H01L29/66 ,  H01L29/51

    CPC分类号： H01L23/53295 ,  H01L23/535 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

    摘要翻译： 本文公开的一种方法包括在凹陷的侧壁间隔物和凹入的替换栅极结构上方形成蚀刻停止层，并且将蚀刻停止层置于适当位置，形成在形成自身之后与源/漏区导电耦合的自对准接触 联系人。 本文公开的装置包括位于凹入的替代栅极结构和凹陷的侧壁间隔物之上的蚀刻停止层，其中蚀刻停止层限定了包含定位在其中的绝缘材料层的蚀刻停止凹部。 该装置还包括自对准接触件。

    FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
    88.
    发明申请
    FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION 有权
    FINFET集成电路及其制造方法

    公开(公告)号：US20150179644A1

    公开(公告)日：2015-06-25

    申请号：US14615762

    申请日：2015-02-06

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

    IPC分类号： H01L27/088 ,  H01L29/06

    CPC分类号： H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

    摘要： Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

    摘要翻译： 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

    Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
    89.
    发明授权
    Selective growth of a work-function metal in a replacement metal gate of a semiconductor device 有权
    在半导体器件的替换金属栅中选择性地生长功函数金属

    公开(公告)号：US09018711B1

    公开(公告)日：2015-04-28

    申请号：US14056144

    申请日：2013-10-17

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092

    CPC分类号： H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

    摘要： Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

    摘要翻译： 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

    INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME
    90.
    发明申请
    INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME 有权
    集成电路，包括具有较低接触电阻和降低的PARASIIC电容的FINFET器件及其制造方法

    公开(公告)号：US20150102422A1

    公开(公告)日：2015-04-16

    申请号：US14551606

    申请日：2014-11-24

    申请人： GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

    IPC分类号： H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L27/088 ,  H01L29/06

    CPC分类号： H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

    摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

    摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。