公开(公告)号：US09865543B1

公开(公告)日：2018-01-09

申请号：US15416152

申请日：2017-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Stan Tsai ,  John H. Zhang ,  Xingzhao Shi ,  Tai Fong Chao

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/82 ,  H01L23/528 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/53209

Abstract: A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive cap is formed using a damascene process by depositing a conductive layer comprising tungsten or copper over a recessed cobalt-based contact, followed by a CMP step to remove excess portions of the conductive layer. The conductive cap can cooperate with a liner/barrier layer to form an effective barrier to cobalt migration and oxidation.

公开(公告)号：US09679985B1

公开(公告)日：2017-06-13

申请号：US15187080

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Haigou Huang

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/42356 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66795

Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US09368342B2

公开(公告)日：2016-06-14

申请号：US14252447

申请日：2014-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Huang Liu ,  Jin Ping Liu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111

Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

Abstract translation: 提供半导体衬底（例如Si）上的无缺陷的，松弛的半导体覆盖层（例如，外延SiGe），其具有高于约80％的应变松弛度和小于约100 / cm 2的非零穿透位错密度 。 衬底和覆盖层之间存在晶格失配。 覆盖层还具有可以小于约0.5微米的非零厚度。 应变松弛度和穿透位错是通过在基板上的初始半导体层的表面处或附近暴露缺陷来实现的（即，通过选择性蚀刻暴露缺陷并填充所产生的任何空隙），平坦化填充表面，以及 在平坦化的填充表面上形成覆盖层（例如，生长外延），其也被平坦化。

公开(公告)号：US20160163830A1

公开(公告)日：2016-06-09

申请号：US14560035

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hong Yu ,  Jin Ping Liu ,  Haigou Huang ,  Huang Liu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02326 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在翅片上形成占位符门结构。 占位符门结构包括在占位符材料的顶表面上限定的占位符材料和盖结构。 盖结构包括设置在占位符材料上方的第一盖层和设置在第一盖层上方的第二盖层。 在第二盖层的至少一部分上进行氧化处理，以在第二盖层的剩余部分上方形成氧化区域。 去除氧化区域的一部分以露出剩余部分。 去除第二盖层的剩余部分。 移除第一盖层以露出占位符材料。 占位符材料被导电材料代替。