公开(公告)号：US20060146614A1

公开(公告)日：2006-07-06

申请号：US11026708

申请日：2004-12-30

Applicant: Hang-Ting Lue ,  Kuang Hsieh

Inventor： Hang-Ting Lue ,  Kuang Hsieh

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0466

Abstract: A raised-Vs Channel Initialed Secondary Electron Injection is disclosed to program a charge-trapping nonvolatile memory cell. The source of the charge-trapping nonvolatile memory cell is applied with a positive source voltage, and the drain of the charge-trapping nonvolatile memory cell is applied with a positive drain voltage, wherein the positive drain voltage is greater than the positive source voltage. The substrate of the charge-trapping nonvolatile memory cell is grounded. A positive gate voltage is applied to the polysilicon gate of the charge-trapping nonvolatile memory cell.

Abstract translation: 公开了一种凸起Vs通道初始二次电子注入来对电荷捕获非易失性存储单元进行编程。 电荷捕获非易失性存储单元的源极被施加正的源极电压，并且电荷俘获非易失性存储单元的漏极被施加正的漏极电压，其中正的漏极电压大于正的源极电压。 电荷捕获非易失性存储单元的衬底接地。 正栅极电压被施加到电荷捕获非易失性存储单元的多晶硅栅极。

公开(公告)号：US20060134866A1

公开(公告)日：2006-06-22

申请号：US11018507

申请日：2004-12-20

Applicant: Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

Inventor： Erh-Kun Lai ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chia-Hua Ho

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

Abstract translation: 提供非易失性存储器。 存储器包括衬底，电介质层，导电层，隔离层，掩埋位线，隧道电介质层，电荷俘获层，势垒介电层和字线。 其中介电层设置在基板上。 导电层设置在电介质层上。 隔离层设置在基板上并且邻近电介质层和导电层。 掩埋位线设置在衬底中并在隔离层下方。 隧道电介质层设置在导电层和隔离层的基板和侧壁上。 电荷捕获层设置在隧道介电层上，势垒介电层设置在电荷俘获层上。 字线设置在基板上，与埋入位线交叉。

公开(公告)号：US09140976B2

公开(公告)日：2015-09-22

申请号：US13619124

申请日：2012-09-14

Applicant: Chih-Chang Hsieh ,  Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Chih-Chang Hsieh ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: G03F1/00 ,  G03F1/36 ,  G11C5/06 ,  G03F1/38 ,  G11C5/02

CPC classification number: G03F1/36 ,  G03F1/38 ,  G11C5/025 ,  G11C5/063

Abstract: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.

Abstract translation: 一种光刻掩模和用于制造这种掩模的方法，其包括光学隔离的特征和接近校正特征。 包括定义通孔的通孔特征的通孔图案以掩模上每行和列之间的行和列间距的行和列定位在掩模上。 通孔图案被定位成使得相邻列中的通孔特征由它们之间的至少一个中间行分开。 通孔图案也可以被定位成使得相邻行中的通孔图案被它们之间的至少一个中间柱隔开。 结果，每个通孔图案的通孔特征和位于每个通孔特征周围的相关联的光学邻近校正特征不与周围通孔图案的光学邻近校正特征和通孔特征重叠。

公开(公告)号：US09035369B2

公开(公告)日：2015-05-19

申请号：US13401634

申请日：2012-02-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/68 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构和第一导电层。 第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。 第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

公开(公告)号：US08922020B2

公开(公告)日：2014-12-30

申请号：US12983832

申请日：2011-01-03

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L23/48 ,  H01L27/115 ,  H01L21/033 ,  H01L23/528

CPC classification number: H01L27/11573 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L27/11565 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract translation: 集成电路图案包括具有X和Y方向部分的一组材料线。 X和Y方向部分具有第一和第二间距，第二间距比第一间距大至少3倍。 X方向部分是平行的，并且Y方向部分是平行的。 Y方向部分的端部区域包括主线部分和偏移部分。 偏移部分包括与主线部分间隔开并电连接到主线部分的偏移元件。 偏移部分限定用于后续图案转印过程的接触区域。 为了在集成电路处理过程中使用的多重图形化方法提供用于随后的图案转印过程的接触区域。

公开(公告)号：US08829646B2

公开(公告)日：2014-09-09

申请号：US12430290

申请日：2009-04-27

Applicant: Hsiang-Lan Lung ,  Hang-Ting Lue

Inventor： Hsiang-Lan Lung ,  Hang-Ting Lue

IPC: H01L23/52 ,  H01L27/102 ,  H01L27/10 ,  H01L27/112

CPC classification number: H01L27/1021 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11582

Abstract: A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.

Abstract translation: 3D存储器件基于电极柱阵列和在包括可编程元件和整流器的存储器元件的界面区域处与电极柱相交的多个电极平面。 可以使用二维解码来选择电极柱，并且可以使用第三维度上的解码来选择多个电极平面。

公开(公告)号：US08811077B2

公开(公告)日：2014-08-19

申请号：US13239760

申请日：2011-09-22

Applicant: Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shih-Hung Chen

Inventor： Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shih-Hung Chen

IPC: G11C5/06 ,  G11C16/04 ,  G11C5/02 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/792

Abstract: A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions.

Abstract translation: 3D集成电路存储器阵列具有多个平面位置。 多个位线结构具有多个平面位置的多个序列。 每个序列表征位线结构将平面位置耦合到位线的顺序。 每个位线耦合到至少两个不同的平面位置以访问两个或更多个不同平面位置处的存储器单元。

公开(公告)号：US08724393B2

公开(公告)日：2014-05-13

申请号：US13458970

申请日：2012-04-27

Applicant: Hang-Ting Lue ,  Chun-Hsiung Hung

Inventor： Hang-Ting Lue ,  Chun-Hsiung Hung

IPC: G11C16/04 ,  G11C16/06 ,  H01L29/00 ,  H01L23/34

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3495 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.

Abstract translation: 存储器包括包括行和列的存储单元阵列。 存储器包括耦合到字线的电路，在施加与第一偏置电压不同的第二偏置电压的同时，将第一偏置电压施加到阵列中的字线或字线上的第一组间隔开的位置， 在字线或字线上的一组间隔开的位置，第一组间隔开的位置中的位置在第二组间隔开的位置中的位置之间交错，从而在第一和第二位置之间的位置之间感应出电流 导致字线或字线加热的位置集合。

公开(公告)号：US08704205B2

公开(公告)日：2014-04-22

申请号：US13594353

申请日：2012-08-24

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

IPC: H01L47/00

CPC classification number: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

Abstract translation: 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

公开(公告)号：US08659944B2

公开(公告)日：2014-02-25

申请号：US13011717

申请日：2011-01-21

Applicant: Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/06

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。