公开(公告)号：US20130328206A1

公开(公告)日：2013-12-12

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

公开(公告)号：US20210013132A1

公开(公告)日：2021-01-14

申请号：US17036271

申请日：2020-09-29

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Giovanni Ragasa Garbin ,  Chen Wen Lee ,  Benjamin Reichert ,  Peter Strobel

IPC: H01L23/495 ,  H01L23/00

Abstract: A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.

公开(公告)号：US10832992B2

公开(公告)日：2020-11-10

申请号：US16518351

申请日：2019-07-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Giovanni Ragasa Garbin ,  Chen Wen Lee ,  Benjamin Reichert ,  Peter Strobel

IPC: H01L21/00 ,  H01L29/40 ,  H01L23/495 ,  H01L23/00

Abstract: A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.

公开(公告)号：US20200352034A1

公开(公告)日：2020-11-05

申请号：US16932925

申请日：2020-07-20

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Joachim Mahler

IPC: H05K3/32 ,  H01L23/488 ,  B22F7/08 ,  B22F7/06 ,  H05K7/02

Abstract: A method includes providing a joining material between a surface of a component and a surface of an electronic component. A plurality of spacer elements is embedded in the joining material. The spacer elements are coated with a coating material. The coating material includes sinter particles. A dimension of the sinter particles is greater than 1 nanometer and smaller than 1000 nanometers. The method further includes forming interconnects from the coating material. The interconnects are arranged between the spacer elements and the surface of the component, and between the spacer elements and the surface of the electronic component.

公开(公告)号：US20200013749A1

公开(公告)日：2020-01-09

申请号：US16572626

申请日：2019-09-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

公开(公告)号：US20190287907A1

公开(公告)日：2019-09-19

申请号：US16279370

申请日：2019-02-19

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg ,  Guenter Tutsch

IPC: H01L23/532 ,  H01L23/31 ,  H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L21/56

Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes an electronic chip and a dielectric structure comprising a highly filled cross-linked thermoplastic material.

公开(公告)号：US10403556B2

公开(公告)日：2019-09-03

申请号：US15381155

申请日：2016-12-16

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Peter Irsigler ,  Joachim Mahler ,  Guenther Ruhl ,  Hans-Joachim Schulze ,  Markus Zundel

IPC: B82Y30/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L23/367 ,  H01L23/373 ,  H01L23/427 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.

公开(公告)号：US10297564B2

公开(公告)日：2019-05-21

申请号：US15725796

申请日：2017-10-05

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Georg Meyer-Berg

IPC: C09J5/06 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  C09J163/00 ,  C09J177/04 ,  C09J179/02 ,  C09J181/00 ,  C09J183/04

Abstract: A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.

公开(公告)号：US09941181B2

公开(公告)日：2018-04-10

申请号：US15599492

申请日：2017-05-19

Applicant: Infineon Technologies AG

Inventor： Heinrich Koerner ,  Michael Bauer ,  Reimund Engl ,  Michael Huettinger ,  Werner Kanert ,  Joachim Mahler ,  Brigitte Ruehle

IPC: H01L23/28 ,  H01L23/29 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/293 ,  H01L21/56 ,  H01L23/295 ,  H01L23/296 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48647 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/365 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2224/45664 ,  H01L2224/45644 ,  H01L2224/45669

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

公开(公告)号：US20180086632A1

公开(公告)日：2018-03-29

申请号：US15704537

申请日：2017-09-14

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Joachim Mahler ,  Daniel Porwol ,  Alfred Sigl

IPC: B81C1/00

CPC classification number: B81C1/00047 ,  B81C1/00666 ,  B81C2201/0125 ,  B81C2201/013 ,  B81C2203/0118 ,  B81C2203/0127

Abstract: A method for fabricating an electronic device is disclosed. In one example, the method comprises providing a semiconductor wafer, forming a plurality of cavities into the semiconductor wafer, filling a stabilization material into the cavities, fabricating a temporary panel by applying a cap sheet onto the semiconductor wafer, the cap sheet covering the cavities, singulating the temporary panel into a plurality of semiconductor devices, fabricating an embedded wafer by embedding the semiconductor devices in an encapsulant, removing the cap sheet of each one of the semiconductor devices, and singulating the embedded wafer into a plurality of electronic devices.