公开(公告)号：US10128180B2

公开(公告)日：2018-11-13

申请号：US15821879

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/12 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56 ,  H01L23/495 ,  H01L23/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

公开(公告)号：US09633927B2

公开(公告)日：2017-04-25

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

公开(公告)号：US20180096924A1

公开(公告)日：2018-04-05

申请号：US15821879

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

公开(公告)号：US20130328206A1

公开(公告)日：2013-12-12

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

公开(公告)号：US10198684B2

公开(公告)日：2019-02-05

申请号：US14719374

申请日：2015-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Frank Pueschner ,  Alfred Haimerl ,  Jens Pohl ,  Wolfgang Schindler

IPC: H01L21/56 ,  G06K19/077 ,  H01L23/498 ,  H01L23/00

Abstract: A smart card module includes a substrate having a first main surface and a second main surface, which is opposite the first main surface. The substrate has a plurality of plated-through holes, which extend through the substrate from the first main surface to the second main surface. The smart card module further includes a chip over the first main surface of the substrate, a first metal structure over the second main surface of the substrate, electrically insulating material, which covers the first metal structure, and a second metal structure over the electrically insulating material, wherein the second metal structure is electrically insulated from the first metal structure by the electrically insulating material. The chip is connected to the first metal structure by at least one first plated-through hole. The chip is connected to the second metal structure by at least one second plated-through hole.

公开(公告)号：US09859198B2

公开(公告)日：2018-01-02

申请号：US14569958

申请日：2014-12-15

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/12 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

公开(公告)号：US20150097282A1

公开(公告)日：2015-04-09

申请号：US14569958

申请日：2014-12-15

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

Abstract translation: 提供芯片封装，芯片封装包括：芯片载体; 芯片布置在芯片载体顶侧并电连接到芯片载体顶侧; 设置在芯片上并且至少部分地围绕芯片的电绝缘材料; 形成在所述电绝缘材料上并与所述芯片电连接的一个或多个导电接触区域; 设置在芯片载体底侧上的另外的电绝缘材料; 其中芯片载体底侧上的导电接触区域从另外的电绝缘材料释放。