公开(公告)号：US08975727B2

公开(公告)日：2015-03-10

申请号：US13721310

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L29/8605 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract translation: 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。

公开(公告)号：US20150056723A1

公开(公告)日：2015-02-26

申请号：US14507209

申请日：2014-10-06

Applicant: Intermolecular, Inc.

Inventor： David E. Lazovsky ,  Tony P. Chiang ,  Sandra G. Malhotra

IPC: H01L21/66

CPC classification number: H01L22/26 ,  H01L21/32051 ,  H01L21/67028 ,  H01L21/6708 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76871

Abstract: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.

Abstract translation: 描述了用于处理具有两个或更多个区域的基板的基板处理系统和方法。 该处理包括分子自组装和组合处理中的一种或多种。 材料，工艺，加工条件，材料应用顺序和工艺顺序中的至少一个不同于衬底相对于衬底的至少一个其它区域的至少一个区域中的处理。 描述了包括许多处理模块的处理系统。 模块包括配置用于衬底的分子自组装和组合处理中的一个或多个的位点隔离反应器（SIR）。

公开(公告)号：US20140353566A1

公开(公告)日：2014-12-04

申请号：US13903656

申请日：2013-05-28

Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

Inventor： Yun Wang ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

Abstract: A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode.

Abstract translation: 用于电阻式开关存储器（ReRAM）的开关元件在高k高离子度可变电阻（VR）材料层和低k低电平层之间突然的结构不连续性时提供可控的一致的灯丝断裂点 活性VR材料。 高离子层可以是结晶的，低离子层可以是无定形的。 低离子层的一致性断点和特性有利于低功率运行。 构成长丝的缺陷（例如，氧或氮空位）起源于高离子性VR层或源电极。 最接近低离子层的电极本质上是惰性的，或者可以有效地使其成为惰性的。 通过在电极上产生低离子层，使一些电极变得有效地是惰性的。

公开(公告)号：US08890109B2

公开(公告)日：2014-11-18

申请号：US13721658

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L47/00 ,  H01L45/00

CPC classification number: H01L45/1293 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元，其包括电阻开关层和用于在操作期间限制来自开关层的散热的热隔离结构。 热隔离结构可以位于堆叠内或邻近堆叠。 例如，堆叠可以包括一个或两个热隔离结构。 热隔离结构可以直接与开关层接口或者可以通过例如电极分离。 热分离结构可以由导热率小于1W / m×K的材料形成，例如多孔二氧化硅和中孔氧化钛。 与开关层串联设置的隔热结构通常具有小于开关层的低电阻状态的电阻。 位于与开关层相邻的隔热结构可具有大于开关层的高电阻状态的电阻。

公开(公告)号：US20140322887A1

公开(公告)日：2014-10-30

申请号：US14325015

申请日：2014-07-07

Applicant: Intermolecular Inc.

Inventor： Michael Miller ,  Tony P. Chiang ,  Xiying Costa ,  Tanmay Kumar ,  Prashant B. Phatak ,  April Schricker

IPC: H01L45/00

CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元结构的方法。 通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。 例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。 在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

公开(公告)号：US08872268B2

公开(公告)日：2014-10-28

申请号：US14163970

申请日：2014-01-24

Applicant: Intermolecular, Inc.

Inventor： Michael Miller ,  Tony P. Chiang ,  Prashant B. Phatak

IPC: H01L27/01 ,  G11C13/00 ,  H01L45/00 ,  H01L21/265 ,  H01L21/322 ,  H01L27/24

CPC classification number: H01L45/122 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/56 ,  H01L21/265 ,  H01L21/322 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L45/1675

Abstract: Controlled localized defect paths for resistive memories are described, including a method for forming controlled localized defect paths including forming a first electrode forming a metal oxide layer on the first electrode, masking the metal oxide to create exposed regions and concealed regions of a surface of the metal oxide, and altering the exposed regions of the metal oxide to create localized defect paths beneath the exposed regions.

Abstract translation: 描述了用于电阻存储器的受控局部缺陷路径，包括用于形成受控局部缺陷路径的方法，包括形成在第一电极上形成金属氧化物层的第一电极，掩蔽金属氧化物以产生暴露区域和隐藏区域 金属氧化物，并且改变金属氧化物的暴露区域以在暴露区域下方产生局部缺陷路径。

公开(公告)号：US20140273300A1

公开(公告)日：2014-09-18

申请号：US14072611

申请日：2013-11-05

Applicant: Intermolecular, Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang

IPC: H01L45/00 ,  H01L21/66

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Abstract translation: 在远高于工作温度的温度下形成电阻式存储器结构可以降低成型电压并产生具有更高稳定性和较低编程电压的缺陷分布。 成型温度高于工作温度200℃。 存储芯片可以包括芯片封装中的嵌入式加热器，从而允许封装后的芯片形成工艺。

公开(公告)号：US20140256111A1

公开(公告)日：2014-09-11

申请号：US14281550

申请日：2014-05-19

Applicant: Intermolecular Inc.

Inventor： Sandra G. Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Wayne R. French ,  Pragati Kumar ,  Prashant B. Phatak ,  Sunil Shanker ,  Wen Wu

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

公开(公告)号：US08816317B2

公开(公告)日：2014-08-26

申请号：US13659037

申请日：2012-10-24

Applicant: Intermolecular, Inc.

Inventor： Alexander Gorer ,  Tony P. Chiang ,  Igor Ivanov ,  Prashant B. Phatak

IPC: H01L47/00

CPC classification number: H01L45/10 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.

Abstract translation: 描述了使用阳极氧化形成的非易失性电阻式开关存储器。 一种使用阳极氧化形成电阻式开关存储元件的方法包括形成含金属层，至少部分地阳极氧化含金属层以形成电阻式开关金属氧化物，以及在电阻式开关金属氧化物上形成第一电极。 在一些实例中，含金属层的未渐变部分可以是存储元件的第二电极。

公开(公告)号：US20140235029A1

公开(公告)日：2014-08-21

申请号：US14259411

申请日：2014-04-23

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Tony P. Chiang

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Abstract translation: 实施例通常包括形成非易失性存储器件的方法，该非易失性存储器件包含通过使用多层可变电阻层而具有改进的器件开关容量的电阻式开关存储器元件。 在一个实施例中，电阻式开关元件包括至少三层可变电阻材料以增加逻辑状态的数量。 每个可变电阻层可以具有相关联的高电阻状态和相关联的低电阻状态。 由于每个可变电阻层的电阻决定了存储的数字数据位，每个存储元件的多个可变电阻层允许额外的数据存储，而不需要进一步增加非易失性存储器件的密度。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。