公开(公告)号：US20200273743A1

公开(公告)日：2020-08-27

申请号：US16286192

申请日：2019-02-26

Applicant: International Business Machines Corporation

Inventor： Kenneth C. K. Cheng ,  Koichi Motoyama ,  Kisik Choi ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532

Abstract: Air-gap containing metal interconnects with selectively-deposited dielectric material are provided. In one aspect, a method of forming an interconnect structure with air-gaps includes: forming interconnect metal lines separated from a first dielectric by a liner and a barrier layer; depositing a capping layer and an inhibitor layer over the interconnect metal lines; patterning the capping layer, inhibitor layer and first dielectric to form the air-gaps between the interconnect metal lines; selectively depositing a second dielectric to form a bridge of the second dielectric over/pinching off the air-gaps, wherein the barrier layer inhibits deposition of the second dielectric along the sidewalls of the interconnect metal lines, and the inhibitor layer inhibits deposition of the second dielectric on top of the interconnect metal lines. An interconnect structure is also provided.

公开(公告)号：US10741609B2

公开(公告)日：2020-08-11

申请号：US16242583

申请日：2019-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gangadhara Raja Muthinti ,  Michael Rizzolo ,  Oscar Van Der Straten ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/14 ,  H01L23/528 ,  H01L23/522 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Integration of structures including an embedded magnetoresistive random access memory (MRAM) device such as a magnetic tunneling junction device includes pre-patterned etch stop layers to prevent excessive etching of the interlayer dielectric during a via open step.

公开(公告)号：US20200251386A1

公开(公告)日：2020-08-06

申请号：US16857408

申请日：2020-04-24

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Terry A. Spooner ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

公开(公告)号：US10714379B2

公开(公告)日：2020-07-14

申请号：US16665471

申请日：2019-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Conal E. Murray ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one electrically conductive feature and forming a shield layer on the opening. A gouge is formed in the electrically conductive feature through the opening using a subtractive method during which the shield layer protects the interlevel dielectric layer from being damaged by the subtractive method. A contact is formed within the opening in electrical communication with the at least one electrically conductive feature.

公开(公告)号：US20200219812A1

公开(公告)日：2020-07-09

申请号：US16242598

申请日：2019-01-08

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L23/525 ,  H01L27/112

Abstract: An electrical fuse (e-fuse) is provided in which the contact area between the fuse element (i.e., fuse link) and the first and second electrodes is reduced. The reduction in contact area provides high electron density and enhanced programming efficiency to the electrical fuse. The fuse element of the present application, which is sandwiched between the first and second electrodes, has a circular ring shape. A dielectric material laterally surrounds the fuse element and is present in the center of the circular ring shaped fuse element.

公开(公告)号：US10672649B2

公开(公告)日：2020-06-02

申请号：US15807156

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Theo Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  C23C18/54 ,  H01L21/321 ,  H01L21/28 ,  C23C18/16 ,  C23C18/38 ,  C25D7/12

Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.

公开(公告)号：US10672611B2

公开(公告)日：2020-06-02

申请号：US16165311

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Michael Rizzolo ,  Ashim Dutta ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L21/033 ,  H01L43/12 ,  H01L43/02

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

公开(公告)号：US20200161239A1

公开(公告)日：2020-05-21

申请号：US16751465

申请日：2020-01-24

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/532

Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.

公开(公告)号：US10658585B2

公开(公告)日：2020-05-19

申请号：US16397502

申请日：2019-04-29

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Lawrence A. Clevenger ,  Chih-Chao Yang ,  Benjamin D. Briggs

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.

公开(公告)号：US10658235B2

公开(公告)日：2020-05-19

申请号：US16014780

申请日：2018-06-21

Applicant: International Business Machines Corporation

Inventor： Prasad Bhosale ,  Terry A. Spooner ,  Chih-Chao Yang ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.