公开(公告)号：US10541128B2

公开(公告)日：2020-01-21

申请号：US15241795

申请日：2016-08-19

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.

公开(公告)号：US20190391481A1

公开(公告)日：2019-12-26

申请号：US16015994

申请日：2018-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yongan Xu ,  Zhenxing Bi ,  Yann Mignot ,  Nelson Felix ,  Ekmini A. De Silva

IPC: G03F1/22 ,  G03F7/20 ,  G03F7/42

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

公开(公告)号：US20190353615A1

公开(公告)日：2019-11-21

申请号：US15985266

申请日：2018-05-21

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Zhenxing Bi

IPC: G01N27/447 ,  B82B3/00 ,  B82B1/00 ,  G01N33/487

Abstract: A method of forming a semiconductor structure includes forming two or more catalyst nanoparticles from a metal layer disposed over a substrate in two or more openings of a hard mask patterned over the metal layer. The method also includes growing two or more carbon nanotubes using the catalyst nanoparticles, and removing the carbon nanotubes to form two or more nanoscale pores. The two or more nanoscale pores may be circular nanoscale pores having a substantially uniform diameter. The two or more openings in the hard mask may have non-uniform size, and the substantially uniform diameter of the two or more nanopores may be controlled by a size of the carbon nanotubes.

公开(公告)号：US10483382B1

公开(公告)日：2019-11-19

申请号：US16278693

申请日：2019-02-18

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Peng Xu ,  Heng Wu ,  Zhenxing Bi

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/45 ,  H01L23/528 ,  H01L21/84 ,  H01L29/78

Abstract: A tunnel field-effect transistor having source and drain contacts made from different electrically conductive materials enables independent optimization of contact resistance on the source and drain sides of the transistor. Dielectric caps on the gate electrode, source contact and drain contact made from different materials allow the selective removal of portions of the caps during gate, source and drain wiring. A wiring strap can be formed across the gate and drain to electrically connect two source contacts together. Multiple drain contacts or multiple gate electrodes may alternatively be electrically connected by wiring straps. Strap wiring facilitates placing transistors in closer proximity to increase the number of transistors for a given chip area.

公开(公告)号：US10475905B2

公开(公告)日：2019-11-12

申请号：US15886539

申请日：2018-02-01

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Zhenxing Bi ,  Kristin Schmidt ,  Yann Mignot

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L29/423 ,  H01L21/3105

Abstract: Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.

公开(公告)号：US20190214311A1

公开(公告)日：2019-07-11

申请号：US16241677

申请日：2019-01-07

Applicant: International Business Machines Corporation

Inventor： Indira Seshadri ,  Ekmini Anuja De Silva ,  Jing Guo ,  Romain J. Lallement ,  Ruqiang Bao ,  Zhenxing Bi ,  Sivananda Kanakasabapathy

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L21/308

CPC classification number: H01L21/823842 ,  H01L21/28185 ,  H01L21/3081 ,  H01L21/8221 ,  H01L21/823821 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7853

Abstract: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.

公开(公告)号：US10347731B2

公开(公告)日：2019-07-09

申请号：US16159673

申请日：2018-10-14

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Heng Wu ,  Peng Xu

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.

公开(公告)号：US10332880B2

公开(公告)日：2019-06-25

申请号：US15807751

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Peng Xu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L49/02 ,  H01L27/06

Abstract: Semiconductor devices and methods are provided in which vertical fin resistor devices are integrally formed as part of a process flow for fabricating FinFET (Fin Field Effect Transistor) devices. For example, a semiconductor device includes a FinFET device and a vertical fin resistor device formed on a semiconductor substrate. The FinFET device includes a vertical semiconductor fin which includes a structural profile that is defined by dimensions of width W, height H, and length L. The vertical fin resistor device includes a vertical fin structure which is formed of a resistive material (e.g., polysilicon or amorphous silicon), and which has a structural profile that is defined by dimension of width W1, height H1, and length L1. The structural profiles of the vertical semiconductor fin of the FinFET device and the vertical fin structure of the vertical fin resistor device have at least one corresponding dimension that is substantially the same.

公开(公告)号：US20190139764A1

公开(公告)日：2019-05-09

申请号：US16236811

申请日：2018-12-31

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234

Abstract: A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

公开(公告)号：US10263075B2

公开(公告)日：2019-04-16

申请号：US15805700

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/324 ,  H01L29/06 ,  H01L25/07 ,  H01L25/00 ,  H01L29/08 ,  H01L21/28

Abstract: Methods of forming integrated chips include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.