公开(公告)号：US20200176321A1

公开(公告)日：2020-06-04

申请号：US16632319

申请日：2017-08-17

Applicant: Intel Corporation

Inventor： Leonard P/ Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US20200098926A1

公开(公告)日：2020-03-26

申请号：US16142940

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/51 ,  H01L27/11585

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

公开(公告)号：US10573747B2

公开(公告)日：2020-02-25

申请号：US15377994

申请日：2016-12-13

Applicant: INTEL CORPORATION

Inventor： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8234

Abstract: Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US20200052117A1

公开(公告)日：2020-02-13

申请号：US16605312

申请日：2017-05-15

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/786

Abstract: Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.

公开(公告)号：US10559744B2

公开(公告)日：2020-02-11

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian Maertz ,  Christopher J. Wiegand ,  Daniel G. Oeullette ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Justin S. Brockman ,  Tahir Ghani ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Kaan Oguz

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US20200044087A1

公开(公告)日：2020-02-06

申请号：US16055634

申请日：2018-08-06

Applicant: INTEL CORPORATION

Inventor： Biswajeet Guha ,  William Hsu ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238

Abstract: Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g., employing one or more nanowires, nanoribbons, or nanosheets), thereby improving device performance.

公开(公告)号：US20200035683A1

公开(公告)日：2020-01-30

申请号：US16043548

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  H01L29/786 ,  H01L23/00 ,  H01L29/417 ,  G11C11/407 ,  G11C7/06

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US10546858B2

公开(公告)日：2020-01-28

申请号：US15579180

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Jack T. Kavalieros ,  Chandra S. Mohapatra ,  Anand S. Murthy ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Tahir Ghani ,  Harold W. Kennel

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L27/06 ,  H01L21/306 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L21/8258 ,  H01L29/205 ,  H01L29/207

Abstract: Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.

公开(公告)号：US10529808B2

公开(公告)日：2020-01-07

申请号：US16072313

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Will Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC: H01L29/417 ,  H01L29/205 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

公开(公告)号：US20190385949A1

公开(公告)日：2019-12-19

申请号：US16464024

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Yih Wang ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L23/528 ,  H01L27/108 ,  G11C5/06

Abstract: Integrated circuit structures are described that include back end memory devices that are integrated into one or more back end interconnect layers of an integrated circuit. Examples of the back end memory devices described include one transistor and one capacitor (“1T/1C”) memory cell devices that use an oxide semiconductor layer (e.g., indium gallium zinc oxide) as an element of the transistor portion (1T) of the back end memory cell. This produces a memory device with a low off state leakage current, improving memory device performance while also reducing memory device size.