公开(公告)号：US06350548B1

公开(公告)日：2002-02-26

申请号：US09526661

申请日：2000-03-15

申请人： Robert K. Leidy ,  Debra L. Meunier

发明人： Robert K. Leidy ,  Debra L. Meunier

IPC分类号： G03F900

CPC分类号： G03F7/70633 ,  H01L22/34 ,  Y10S438/975

摘要： A mask overlay measurement target includes nested boxes on three levels or has adjacent boxes sharing a common side, saving substantial area. The nested overlay measurement target also provides savings in measurement time since multiple overlay combinations can be measured at once. The nested target provides more level-to-level overlay information than has been available with standard box-in-box targets. The nested boxes are also used on a single level to provide area savings for stepper field placement metrology.

摘要翻译： 掩模覆盖测量目标包括三个级别的嵌套框架或具有共享共同侧面的相邻框架，从而节省大量面积。 嵌套覆盖测量目标还可以节省测量时间，因为可以一次测量多个叠加组合。 嵌套的目标提供了比标准框中的目标可用的更多的级别到级别的覆盖信息。 嵌套盒也用于单个级别，以提供步进场放置度量的面积节省。

公开(公告)号：US5959325A

公开(公告)日：1999-09-28

申请号：US917009

申请日：1997-08-21

申请人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

发明人： William J. Adair ,  Richard A. Ferguson ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  William Hsioh-Lien Ma ,  Ronald M. Martino ,  Song Peng

IPC分类号： H01L21/033 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/0332 ,  H01L21/0334 ,  Y10S438/942

摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

摘要翻译： 公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案 到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。 提出了用于显影方形交叉区域和由开口限定的方角区域的方法。 此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。

公开(公告)号：US5861330A

公开(公告)日：1999-01-19

申请号：US852466

申请日：1997-05-07

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

公开(公告)号：US20100029021A1

公开(公告)日：2010-02-04

申请号：US12182668

申请日：2008-07-30

申请人： Brent A. Anderson ,  Robert K. Leidy ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Robert K. Leidy ,  Jed H. Rankin

IPC分类号： H01L21/66

CPC分类号： G03F7/70866 ,  G03F7/7085 ,  G03F7/70975

摘要： Methods for real-time contamination, environmental, or physical monitoring of a photomask. An attribute of a photomask is monitored using a sensor of an electronics package attached to the photomask. The methods further include generating one or more sensor signals relating to the monitored attribute with the sensor and transmitting the one or more sensor signals from the electronics package to a control system.

摘要翻译： 光掩模的实时污染，环境或物理监测的方法。 使用附接到光掩模的电子封装的传感器监视光掩模的属性。 所述方法还包括利用所述传感器生成与所监视的属性相关的一个或多个传感器信号，并将所述一个或多个传感器信号从所述电子装置封装传送到控制系统。

公开(公告)号：US20080315124A1

公开(公告)日：2008-12-25

申请号：US11767633

申请日：2007-06-25

申请人： Robert K. Leidy ,  Paul D. Sonntag ,  Peter J. Sullivan

发明人： Robert K. Leidy ,  Paul D. Sonntag ,  Peter J. Sullivan

IPC分类号： G21G5/00

CPC分类号： G03F7/70475 ,  G03F7/70466 ,  Y10S430/143

摘要： A method for manufacturing a stitched space in a semiconductor circuit implements a photolithographic process for printing one or more image fields on a wafer surface, each image field corresponding to a portion of a circuit or device and including a space that is to be stitched in adjacent image fields. The space to be stitched that is produced from an image field is overlapped onto the space to be stitched produced from the adjacent image field, however, the overlapped space from the adjacent image fields is intentionally misaligned. The stitched space is then subject to the double light exposure dose to print the stitched space, with the result that an overlay tolerance of the stitched space is improved.

摘要翻译： 用于制造半导体电路中的缝合空间的方法实现了用于在晶片表面上印刷一个或多个图像场的光刻工艺，每个图像场对应于电路或器件的一部分，并且包括将被相邻的缝合空间 图像字段。 从图像场产生的要缝制的空间被重叠在从相邻图像场产生的待缝合的空间上，然而，与相邻图像场的重叠空间被有意地对准。 然后缝合的空间经受双倍曝光剂量以打印缝合空间，结果是改善了缝合空间的覆盖公差。

公开(公告)号：US07176485B2

公开(公告)日：2007-02-13

申请号：US10920936

申请日：2004-08-18

申请人： Robert K. Leidy

发明人： Robert K. Leidy

IPC分类号： H01L23/532

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

摘要翻译： 提供了一种用于确定在绝缘体中形成的镶嵌金属线的线宽的线宽测量结构。 所述线宽测量结构包括：形成在所述绝缘体中的镶嵌多晶硅线，所述多晶硅线具有具有预定电阻率的掺杂区域。

公开(公告)号：US06944578B2

公开(公告)日：2005-09-13

申请号：US10868411

申请日：2004-06-15

申请人： Reginald R. Bowley, Jr. ,  Vincent J. Carlos ,  James E. Doran ,  Stephen E. Knight ,  Robert K. Leidy ,  Keith J. Machia ,  Joseph E. Shaver ,  Dianne L. Sundling

发明人： Reginald R. Bowley, Jr. ,  Vincent J. Carlos ,  James E. Doran ,  Stephen E. Knight ,  Robert K. Leidy ,  Keith J. Machia ,  Joseph E. Shaver ,  Dianne L. Sundling

IPC分类号： G03F7/20 ,  G03F9/02 ,  G03C5/00

CPC分类号： G03F7/70625 ,  G03F7/70641

摘要： A method uses three dimensional feature metrology for implementation of critical image control and feedback of lithographic focus and x/y tilt. The method is for measuring 3 dimensional profile changes in a photo sensitive film and feeding back compensatory exposure tool focus corrections to maintain a stable lithographic process. The measured focus change from the optimal tool focus offset is monitored directly on the critical product images for both contact hole and line images. Z Focus corrections and x/y tilt corrections are fed back independently of dose to maintain critical dimension (CD) control. Additionally, the method can be used to diagnose problems with the focusing system by measuring the relationship between line edge width and barometric pressure.

摘要翻译： 一种方法使用三维特征计量来实现关键图像控制和光刻焦点和x / y倾斜的反馈。 该方法用于测量光敏膜中的三维轮廓变化，并反馈补偿曝光工具对焦校正以保持稳定的光刻过程。 从最佳工具对焦偏移测量的焦点变化直接监测接触孔和线图像的关键产品图像。 Z独立于剂量反馈对焦校正和x / y倾斜校正以维持关键尺寸（CD）控制。 此外，该方法可用于通过测量线边宽度和大气压力之间的关系来诊断聚焦系统的问题。

公开(公告)号：US06749969B2

公开(公告)日：2004-06-15

申请号：US09992767

申请日：2001-11-14

申请人： David V. Horak ,  Robert K. Leidy

发明人： David V. Horak ,  Robert K. Leidy

IPC分类号： G03F900

CPC分类号： G03F1/68 ,  G03F1/36

摘要： A reverse image mask is produced by initially depositing a metallic layer on a substrate. Resist is applied to the metallic layer to pattern desired features. The metallic layer is plated with a metal film, and the resist is then stripped. The metallic layer is etched using the metal film as a mask. Finally, the metal film is etched leaving the metallic layer etched in patterned areas to provide the reverse image mask.

摘要翻译： 通过最初在基底上沉积金属层来产生反向图像掩模。 将抗蚀剂施加到金属层以图案化所需特征。 金属层镀金属膜，然后剥离抗蚀剂。 使用金属膜作为掩模蚀刻金属层。 最后，蚀刻金属膜，留下在图案化区域中蚀刻的金属层，以提供反向图像掩模。

公开(公告)号：US06344373B1

公开(公告)日：2002-02-05

申请号：US09106980

申请日：1998-06-29

申请人： Arup Bhattacharyya ,  Robert M. Geffken ,  Chung H. Lam ,  Robert K. Leidy

发明人： Arup Bhattacharyya ,  Robert M. Geffken ,  Chung H. Lam ,  Robert K. Leidy

IPC分类号： H01L2182

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.

摘要翻译： 根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。 优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。 可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。 两层芯优选包括注入层和电介质层。 注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。 最初，喷射器层和电介质层是不导电的。 当施加足够的电压时，芯保持在一起并变得导电。

公开(公告)号：US06218704B1

公开(公告)日：2001-04-17

申请号：US08851973

申请日：1997-05-07

申请人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L2362

CPC分类号： H01L27/0288 ,  H01L27/0255 ,  H01L29/1083 ,  H01L2924/0002 ,  H01L2924/00

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the robustness of electrostatic discharge (ESD) protection devices by reducing the temperature gradient caused by ESD pulses and reducing the likelihood of thermal runaway caused by large ESD pulses. The preferred embodiment forms implants under the trench isolation structures in the ESD devices. The implants reduce the current-caused heating that can lead to thermal runaway, and thus improve the robustness of the ESD protection device. In the preferred embodiment, the implants are formed using hybrid resist. The hybrid resist provides a method to form that implants that does not require additional masking steps or other excessive processing. Additionally, the hybrid resist provides implants that are self aligned with the well regions.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过降低ESD脉冲引起的温度梯度并降低由于静电放电（ESD）保护装置引起的热失控的可能性而增加静电放电（ESD）保护装置的鲁棒性的装置和方法 大ESD脉冲。 优选实施例在ESD器件中的沟槽隔离结构之下形成植入物。 植入物减少导致热失控的电流引起的加热，从而提高ESD保护装置的鲁棒性。 在优选实施例中，使用混合抗蚀剂形成植入物。 混合抗蚀剂提供了形成不需要额外掩蔽步骤或其它过量处理的植入物的方法。 此外，混合抗蚀剂提供与阱区自对准的植入物。