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公开(公告)号：US06344373B1
公开(公告)日：2002-02-05
申请号：US09106980
申请日：1998-06-29
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译： 根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。 优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。 可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。 两层芯优选包括注入层和电介质层。 注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。 最初，喷射器层和电介质层是不导电的。 当施加足够的电压时，芯保持在一起并变得导电。
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公开(公告)号：US5811870A
公开(公告)日：1998-09-22
申请号：US850033
申请日：1997-05-02
IPC分类号： H01L21/82 , H01L23/525 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译： 根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。 优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。 可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。 两层芯优选包括注入层和电介质层。 注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。 最初，喷射器层和电介质层是不导电的。 当施加足够的电压时，芯保持在一起并变得导电。
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3.发明授权Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权需要单极编程的双极型二极管三维存储器的解码方案公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译： 一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。 示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。 该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。 该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。
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公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译： 一种用于感测内容可寻址存储器中匹配线的感测电路和方法。 感测电路包括电反馈回路中电耦合到匹配线的反相器。 逆变器包括匹配线的反相阈值。 在预充电阶段期间，将匹配线充电至基本上第一电压阈值。 当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。
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公开(公告)号：US20140052900A1
公开(公告)日：2014-02-20
申请号：US13610830
申请日：2012-09-11
申请人： Bing Dai , Chung H. Lam , Jing Li
发明人： Bing Dai , Chung H. Lam , Jing Li
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F1/32 , G06F12/0246
摘要： A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).
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公开(公告)号：US20130314983A1
公开(公告)日：2013-11-28
申请号：US13478932
申请日：2012-05-23
申请人： Chung H. Lam , Jing Li , Binquan Luan , Glenn J. Martyna , Dennis M. Newns
发明人： Chung H. Lam , Jing Li , Binquan Luan , Glenn J. Martyna , Dennis M. Newns
CPC分类号： G11C11/16 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/009 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A method of storing a bit at a memory device is disclosed. A memory cell the memory device is formed of a germanium-deficient chalcogenide glass configured to alternate between an amorphous phase and a crystalline phase upon application of a selected voltage, wherein a drift coefficient of the germanium-deficient chalcogenide glass is less than a drift coefficient of an undoped chalcogenide glass. A voltage is applied to the formed memory cell to select one of the amorphous phase and the crystalline phase to store the bit.
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公开(公告)号：US08536675B2
公开(公告)日：2013-09-17
申请号：US13364153
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
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公开(公告)号：US08421194B2
公开(公告)日：2013-04-16
申请号：US13006403
申请日：2011-01-13
IPC分类号： H01L29/06
CPC分类号： H01L21/0337
摘要： A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.
摘要翻译： 沟槽结构和集成电路，其包括衬底中的次光刻沟槽结构。 在一个实施例中，沟槽结构是通过用光刻掩膜形成一组沟槽而形成的，并且用一组间隔块块填充该组沟槽，该组间隔块包括彼此分离地可拆卸的两个交替间隔物材料。 在一个实施例中，形成的沟槽结构是光刻掩模的特征尺寸的厚度的十分之一。 沟槽结构的尺寸取决于用于形成一组步进间隔块的间隔材料层的厚度和数量。 间隔材料层的数量为n / 2，每个间隔材料层的厚度为光刻掩模的特征尺寸的十分之一。
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公开(公告)号：US20130039110A1
公开(公告)日：2013-02-14
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译： 用于在两层半导体晶片上制造存储器件的存储器件和方法。 示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。 此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。 另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造 晶圆。
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公开(公告)号：US08338225B2
公开(公告)日：2012-12-25
申请号：US13350817
申请日：2012-01-16
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1683
摘要： A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.
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