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266 条记录 (耗时 0.031 秒)

    Systems involving spin-transfer magnetic random access memory
    82.
    发明授权
    Systems involving spin-transfer magnetic random access memory 有权
    涉及自旋转移磁随机存取存储器的系统

    公开(公告)号：US07505308B1

    公开(公告)日：2009-03-17

    申请号：US12118441

    申请日：2008-05-09

    申请人： Solomon Assefa ,  William J. Gallagher ,  Chung H. Lam ,  Jonathan Z. Sun

    发明人： Solomon Assefa ,  William J. Gallagher ,  Chung H. Lam ,  Jonathan Z. Sun

    IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673

    摘要： An exemplary magnetic random access memory system comprising, a spin-current generating portion including, a ferromagnetic film layer, and a conductance layer, a first write portion in electrical contact with the ferromagnetic film including, a selection device, and a first read portion in electrical contact with the conductance layer including, a free layer magnet, a read non-magnetic layer, and a reference layer, a second write portion in electrical contact with the ferromagnetic film, and a second read portion in electrical contact with the conductance layer.

    摘要翻译： 一种示例性磁性随机存取存储器系统，包括：自旋电流产生部分，包括铁磁膜层和电导层，与铁磁膜电接触的第一写入部分，包括选择装置，以及第一读取部分， 与电导层电接触，包括自由层磁体，读非磁性层和参考层，与铁磁膜电接触的第二写入部分和与导电层电接触的第二读取部分。

    Multi-bit error correction scheme in multi-level memory storage system
    84.
    发明申请
    Multi-bit error correction scheme in multi-level memory storage system 有权
    多级存储系统中的多位纠错方案

    公开(公告)号：US20090013231A1

    公开(公告)日：2009-01-08

    申请号：US11772347

    申请日：2007-07-02

    申请人： Chung H. Lam

    发明人： Chung H. Lam

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1072 ,  G11C11/56 ,  G11C29/00

    摘要： A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value. The retrieved count, equal to the number of occurrences the binary multi-bit value, is retrieved from the memory cell collection. The stored count, equal to the number of occurrences the binary multi-bit value, is stored in the memory cell collection. An error correction unit then assigns the error memory cell(s) a corrected binary multi-bit value with the characteristic parameter value within the characteristic parameter band adjacent to the characteristic parameter band associated with the retrieved binary multi-bit value such that the retrieved count of each binary multi-bit value is equal to the stored count of each binary multi-bit value.

    摘要翻译： 用于操作存储器单元集合的方法，系统和计算机软件产品。 集合中的存储单元存储由特征参数的特征参数带分隔的二进制多位值。 在一个实施例中，比较单元比较每个二进制多位值的检索计数和存储的计数。 从存储单元集合中检索到与二进制多位值的出现次数相等的检索计数。 存储的计数等于二进制多位值的出现次数存储在存储单元集合中。 纠错单元然后将错误存储器单元分配给具有与所检索的二进制多位值相关联的特性参数带相邻的特征参数频带内的特性参数值的校正二进制多位值，使得检索到的计数 每个二进制多位值的值等于每个二进制多位值的存储计数。

    SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS
    85.
    发明申请
    SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS 有权
    使用可编程的开关阵列电路和系统，具有相变材料的结构

    公开(公告)号：US20080277644A1

    公开(公告)日：2008-11-13

    申请号：US11745811

    申请日：2007-05-08

    申请人： Kuan-Neng Chen ,  Chung H. Lam

    发明人： Kuan-Neng Chen ,  Chung H. Lam

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H03K19/1736

    摘要： The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided.

    摘要翻译： 本发明提供至少一个可编程通孔结构，其包括直接接触加热元件的至少两个相变材料通孔，所述可编程通孔结构还包括与加热元件的第一部分接触的第一端子，第二 与所述加热元件的第二部分接触的端子，与所述至少两个可编程通孔中的一个接触的第三端子以及与所述至少两个可编程通孔中的另一个接触的第四端子; 与所述第三和第四端子中的一个接触的第一电路块; 与不与第一电路块接触的第三或第四端子接触的第二电路块; 与所述第一和第二端子中的一个接触的第一场效应晶体管的源极区域; 以及与不与第一场效应晶体管的源极区域接触的第一或第二端子接触的第二场效应晶体管的漏极区域。 还提供了一种操作至少一个可编程通孔结构的方法。

    FOUR-TERMINAL PROGRAMMABLE VIA-CONTAINING STRUCTURE AND METHOD OF FABRICATING SAME
    86.
    发明申请
    FOUR-TERMINAL PROGRAMMABLE VIA-CONTAINING STRUCTURE AND METHOD OF FABRICATING SAME 有权
    四端可编程的通用结构及其制造方法

    公开(公告)号：US20080251778A1

    公开(公告)日：2008-10-16

    申请号：US11733523

    申请日：2007-04-10

    申请人： Kuan-Neng Chen ,  Chung H. Lam

    发明人： Kuan-Neng Chen ,  Chung H. Lam

    IPC分类号： H01L47/00 ,  H01L21/44

    CPC分类号： H01L45/148 ,  H01L23/525 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683 ,  H01L2924/0002 ,  Y10S438/90 ,  H01L2924/00

    摘要： A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure.

    摘要翻译： 一种半导体结构，其包括两个可编程通孔，每个可编程通孔包含与加热材料集成的相变材料。 特别地，本发明提供一种结构，其中每个包含相变材料的两个可编程通孔位于加热材料的相对表面上。 加热材料的上表面的每个端部连接到金属端子。 与加热材料的上表面的端部接触的这些金属端子可以各自连接到控制和切换两个可编程通孔的电阻状态的外部部件。 本发明结构的两个可编程通孔各自连接到另一金属端子。 与可编程通孔相关联的这些金属端子也可以连接到可能存在于结构中的电路块。

    Antifuse structure and process
    89.
    发明授权
    Antifuse structure and process 失效
    形成反熔丝的方法

    公开(公告)号：US06344373B1

    公开(公告)日：2002-02-05

    申请号：US09106980

    申请日：1998-06-29

    申请人： Arup Bhattacharyya ,  Robert M. Geffken ,  Chung H. Lam ,  Robert K. Leidy

    发明人： Arup Bhattacharyya ,  Robert M. Geffken ,  Chung H. Lam ,  Robert K. Leidy

    IPC分类号： H01L2182

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.

    摘要翻译： 根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。 优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。 可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。 两层芯优选包括注入层和电介质层。 注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。 最初，喷射器层和电介质层是不导电的。 当施加足够的电压时，芯保持在一起并变得导电。

    Antifuse structure
    90.
    发明授权
    Antifuse structure 失效
    防腐结构

    公开(公告)号：US5811870A

    公开(公告)日：1998-09-22

    申请号：US850033

    申请日：1997-05-02

    申请人： Arup Bhattacharyya ,  Robert M. Geffken ,  Chung H. Lam ,  Robert K. Leidy

    发明人： Arup Bhattacharyya ,  Robert M. Geffken ,  Chung H. Lam ,  Robert K. Leidy

    IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L29/04

    CPC分类号： H01L23/5252 ,  H01L2924/0002

    摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.

    摘要翻译： 根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。 优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。 可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。 两层芯优选包括注入层和电介质层。 注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。 最初，喷射器层和电介质层是不导电的。 当施加足够的电压时，芯保持在一起并变得导电。