利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

189 条记录 (耗时 0.04 秒)

    Semiconductor memory device
    81.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5943284A

    公开(公告)日：1999-08-24

    申请号：US705315

    申请日：1996-08-29

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02B60/1225

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    SYSTEM FOR DIAGNOSING CHRONIC PAIN-RELATED DISEASES AND DISEASES REQUIRING DIFFERENTIATION THEREFROM
    82.
    发明申请
    SYSTEM FOR DIAGNOSING CHRONIC PAIN-RELATED DISEASES AND DISEASES REQUIRING DIFFERENTIATION THEREFROM 审中-公开

    公开(公告)号：US20190209081A1

    公开(公告)日：2019-07-11

    申请号：US16333602

    申请日：2017-09-15

    申请人： Kenichi Osada

    发明人： Kenichi Osada

    IPC分类号： A61B5/00 ,  A61B5/16

    CPC分类号： A61B5/483 ,  A61B5/165 ,  A61B5/4827 ,  A61B5/7246 ,  A61B10/00

    摘要： The present invention addresses the problem of providing a system and a method for noninvasively and conveniently diagnosing difficult-to-diagnose chronic pain-related diseases and/or diseases requiring differentiation from the chronic pain-related diseases. The problem was solved by providing a method for obtaining an indicator for determining the presence and/or type of a chronic pain-related disease and/or disease requiring differentiation from chronic pain-related diseases, the method comprising: (a) performing an offset measurement test of pain on a subject that does not suffer from a neurological disorder; (b) analyzing the results obtained from the test in (a); and (c) comparing the analysis results obtained in (b) with a reference value.

    Semiconductor device comprising stacked LSI having circuit blocks connected by power supply and signal line through vias
    84.
    发明授权
    Semiconductor device comprising stacked LSI having circuit blocks connected by power supply and signal line through vias 失效
    半导体器件包括具有通过电源连接的电路块和通过通孔的信号线的堆叠LSI

    公开(公告)号：US08653645B2

    公开(公告)日：2014-02-18

    申请号：US13388990

    申请日：2009-09-14

    申请人： Masanao Yamaoka ,  Kenichi Osada

    发明人： Masanao Yamaoka ,  Kenichi Osada

    IPC分类号： H01L23/52

    CPC分类号： H01L22/30 ,  H01L23/50 ,  H01L23/5286 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An object of the present invention is to sufficiently supply power to three-dimensionally stacked LSI chips and to dispose common through vias in chips of different types. Also, another object is to propose a new test method for power-supply through silicon vias. In order to achieve these objects, a semiconductor device includes: a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction; a plurality of signal-line through vias that are connected to the first semiconductor substrate and transmit signals, which are output from the first circuit block, to a second circuit block formed on another second semiconductor substrate; and a plurality of power-supply through vias for supplying power to the first circuit block, and in the semiconductor device, the plurality of power-supply through vias are formed at edges of the first semiconductor substrate along the third and fourth sides and are formed in a plurality of rows in the first direction. Also, each of the circuit blocks has a power consuming mode in which power larger than the power consumption in a normal mode is consumed.

    摘要翻译： 本发明的目的是为三维堆叠的LSI芯片充分供电，并在通常的通孔中配置不同类型的芯片。 此外，另一个目的是提出一种通过硅通孔供电的新测试方法。 为了实现这些目的，半导体器件包括：第一电路块，形成在第一半导体衬底上，第一半导体衬底具有沿第一方向延伸的第一和第二侧面，以及沿与第一方向相交的第二方向延伸的第三和第四侧面; 连接到第一半导体衬底并将从第一电路块输出的发射信号的多个信号线通孔传送到形成在另一第二半导体衬底上的第二电路块; 以及多个用于向第一电路块提供电力的通孔的供电通道，并且在半导体器件中，多个电源通孔沿着第三和第四侧形成在第一半导体衬底的边缘处，并且形成 在第一方向上的多行中。 此外，每个电路块具有消耗大于正常模式下的功率消耗的功率的功耗模式。

    Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes
    85.
    发明授权
    Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权
    半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元

    公开(公告)号：US08482083B2

    公开(公告)日：2013-07-09

    申请号：US12821329

    申请日：2010-06-23

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L29/76 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低 导致出现微图案化困难的问题。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

    Semiconductor device
    86.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08242589B2

    公开(公告)日：2012-08-14

    申请号：US13148993

    申请日：2009-02-27

    申请人： Makoto Saen ,  Kenichi Osada ,  Kiyoto Ito

    发明人： Makoto Saen ,  Kenichi Osada ,  Kiyoto Ito

    IPC分类号： H01L23/02

    CPC分类号： G01R31/318513 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L2224/16145 ,  H01L2224/16225

    摘要： In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods. Therefore, for a device test of a Through Silicon Via through a plurality of chips, a circuit that generates a time-series test pattern having both 0 and 1 values for a delay fault test is added to a circuit portion that transmits data to a Through Silicon Via in the stacked LSIs, and a circuit that receives the test pattern and compares the pattern received with a fixed pattern for a match to detect a defect of a Through Silicon Via is added to a circuit portion that receives data from a Through Silicon Via in the stacked LSIs.

    摘要翻译： 在通过硅通孔连接的层叠LSI的测试方法中，仅通过使用传统的器件测试方法仅对硅晶片的一侧进行故障诊断是困难的，因此在LSI的堆叠时间内产生劣化的可能性 ，并且多个LSI连接到一个通硅通孔，使得有必要考虑到所有器件状态来选择和补救有缺陷的Through Silicon Via。 这些问题不能用传统的测试方法来解决。 因此，对于通过多个芯片的通孔硅器件的器件测试，产生用于延迟故障测试的具有0和1值的时间序列测试图案的电路被添加到电路部分，该电路部分将数据发送到通 在层叠的LSI中的硅通孔，以及接收测试图案并将接收的模式与用于匹配的固定模式进行比较以检测通硅通孔的缺陷的电路被添加到从直通硅通道接收数据的电路部分 在堆叠的LSI中。

    Semiconductor apparatus
    87.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08184463B2

    公开(公告)日：2012-05-22

    申请号：US12636758

    申请日：2009-12-13

    申请人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    发明人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

    IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

    摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

    摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

    Semiconductor device and semiconductor integrated circuit
    88.
    发明授权
    Semiconductor device and semiconductor integrated circuit 有权
    半导体器件和半导体集成电路

    公开(公告)号：US08054871B2

    公开(公告)日：2011-11-08

    申请号：US12370338

    申请日：2009-02-12

    申请人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

    发明人： Makoto Saen ,  Kenichi Osada ,  Shigenobu Komatsu ,  Itaru Nonomura ,  Yasuhisa Shimazaki

    IPC分类号： H04L5/16 ,  H04B1/38

    CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

    摘要： A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

    摘要翻译： 一种半导体器件，包括能够通过无线彼此通信的一对叠层半导体IC。 每个IC具有：发射机电路，其可操作来通过无线发送数据与决定发送定时的时钟信号一起发送，并且被布置成使得无线发送定时是可调节的; 接收机电路，可操作以与由无线接收的时钟信号同步地接收数据，并且被布置为使得其无线接收定时是可调节的; 以及控制电路，其可操作以基于由所述另一IC响应于通过所述发射机电路发送的数据并由所述接收机电路接收的数据的认证的结果执行所述发射机和接收机电路的定时调整。 用于层叠半导体IC之间的近场通信的这种布置使得能够减少用于通信定时调整的电路的规模; 并高度准确地调整通讯时机。

    Semiconductor integrated circuit and semiconductor device with the same
    90.
    发明授权
    Semiconductor integrated circuit and semiconductor device with the same 有权
    半导体集成电路和半导体器件相同

    公开(公告)号：US07849237B2

    公开(公告)日：2010-12-07

    申请号：US12172512

    申请日：2008-07-14

    申请人： Itaru Nonomura ,  Makoto Saen ,  Kenichi Osada

    发明人： Itaru Nonomura ,  Makoto Saen ,  Kenichi Osada

    IPC分类号： G06F13/12

    CPC分类号： G06F13/4045 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.

    摘要翻译： 一种互连配置技术，其通过使用3D耦合技术发送和接收通过内置在半导体芯片中的互连的芯片传输的分组，从安装在半导体芯片上的IP到安装在另一半导体芯片上的IP进行访问。 根据该技术的设备具有用于发送接入请求的发起者，用于接收接入请求并发送接入响应的目标，用于中继接入请求和接入响应的路由器，以及3D耦合电路（三维收发机 ），用于与外部进行通信，其中所述3D耦合电路邻近所述路由器设置。