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公开(公告)号：US20070096972A1
公开(公告)日：2007-05-03
申请号：US11641656
申请日：2006-12-20
申请人： Shigeto Kobayashi , Atsushi Wada
发明人： Shigeto Kobayashi , Atsushi Wada
IPC分类号： H03M1/12
摘要： The present invention provides a technique for reducing power consumption of an A/D converting device. An A/D converting device according to the present invention includes: multiple comparators each of which has a function for comparing input analog signals with a predetermined reference voltage; an A/D converter for converting the input analog signal into the digital signal with a predetermined number of bits using comparison results from the multiple comparators; a determining unit for determining which range the voltage of the input analog signal belongs to before the comparators comparing the input analog signal with the reference voltages; and a control unit for controlling power supply for the multiple comparators corresponding to the range determined by the determining unit. Thus, power is supplied only to the comparators necessary for this particular A/D conversion, thereby reducing power consumption.
摘要翻译： 本发明提供一种用于降低A / D转换装置的功耗的技术。 根据本发明的A / D转换装置包括：多个比较器，每个比较器具有将输入模拟信号与预定参考电压进行比较的功能; A / D转换器，用于使用来自多个比较器的比较结果将输入的模拟信号转换成具有预定位数的数字信号; 确定单元，用于在比较器将输入模拟信号与参考电压进行比较之前确定输入模拟信号的电压属于哪个范围; 以及控制单元，用于控制对应于由确定单元确定的范围的多个比较器的电源。 因此，仅向该特定A / D转换所需的比较器供电，从而降低功耗。
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公开(公告)号：US07187311B2
公开(公告)日：2007-03-06
申请号：US11206907
申请日：2005-08-19
申请人： Atsushi Wada , Kuniyuki Tani
发明人： Atsushi Wada , Kuniyuki Tani
IPC分类号： H03M1/10
摘要： An AD converter capable of achieving both an improved processing speed and a reduced circuit area in good balance. The AD converter pipelines analog-to-digital conversion by using a two-stage configuration consisting of a first conversion unit, or the prior stage, and a second conversion unit, or the subsequent stage. The first conversion unit is a conversion unit of noncyclic type. The second conversion unit is a conversion unit of cyclic type. The second conversion unit is given a conversion processing speed higher than that of the first conversion unit so that the second conversion unit performs cyclic processing twice while the first conversion unit performs conversion processing once.
摘要翻译： AD转换器能够以良好的平衡实现提高的处理速度和减小的电路面积。 AD转换器通过使用由第一转换单元或前一级以及第二转换单元或后续级组成的两级配置来管线模数转换。 第一转换单元是非循环型转换单元。 第二转换单元是循环型转换单元。 给予第二转换单元的转换处理速度高于第一转换单元的转换处理速度，使得第二转换单元在第一转换单元执行转换处理一次的同时进行两次循环处理。
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公开(公告)号：US07173556B2
公开(公告)日：2007-02-06
申请号：US11073720
申请日：2005-03-08
申请人： Shigeto Kobayashi , Atsushi Wada , Kuniyuki Tani
发明人： Shigeto Kobayashi , Atsushi Wada , Kuniyuki Tani
IPC分类号： H03M1/38
CPC分类号： H03M1/1225 , H03M1/167
摘要： One or more input capacitors are connected to an inverting input terminal of an operational amplifier. Connected to the respective input capacitors are switches for on-off control of the input of an input signal, switches for on-off control of the input of another input signal, switches for on-off control of the input of a higher reference voltage and switches for on-off control of the input of a lower reference voltage. The switches for on-off control of the input of an input signal and the switches for on-off control of the input of another input signal are controlled by independent control signals.
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公开(公告)号：US07119728B2
公开(公告)日：2006-10-10
申请号：US11061668
申请日：2005-02-22
申请人： Atsushi Wada , Kuniyuki Tani , Shigeto Kobayashi
发明人： Atsushi Wada , Kuniyuki Tani , Shigeto Kobayashi
IPC分类号： H03M1/12
摘要： The present invention provides a widely general-purpose A/D converting device. The A/D converting device comprises multiple signal conversion units each of which include: an A/D converter for converting an input analog signal into a digital signal with a predetermined number of bits; a D/A converter for converting the output from the A/D converter into an analog signal; a subtracter for subtracting the output signal from the D/A converter, from the input analog signal; and an amplifier for amplifying the output signal from the subtracter. The A/D converting device has a configuration wherein the signal conversion units are arrayed in multiple rows and columns. This allows the user to realize an A/D converting device having various types and levels of performance by making various combinations of the signal conversion units without change of the layout of the signal conversion units.
摘要翻译： 本发明提供广泛通用的A / D转换装置。 A / D转换装置包括多个信号转换单元，每个信号转换单元包括：A / D转换器，用于将输入的模拟信号转换成具有预定位数的数字信号; 用于将来自A / D转换器的输出转换为模拟信号的D / A转换器; 用于从输入模拟信号中减去D / A转换器的输出信号的减法器; 以及用于放大来自减法器的输出信号的放大器。 A / D转换装置具有其中信号转换单元以多行和列排列的配置。 这允许用户通过进行信号转换单元的各种组合而不改变信号转换单元的布局来实现具有各种类型和级别的性能的A / D转换装置。
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公开(公告)号：US20060187105A1
公开(公告)日：2006-08-24
申请号：US11354245
申请日：2006-02-15
申请人： Kohji Sakata , Seiichi Banba , Atsushi Wada
发明人： Kohji Sakata , Seiichi Banba , Atsushi Wada
IPC分类号： H03M1/12
摘要： An analog-to-digital conversion apparatus which has a variable resolution and allows a reduction in power consumption. This apparatus comprises an analog-to-digital converter (ADC) of parallel type, a controller, and an interpolation circuit. The analog-to-digital converter has a plurality of comparators connected in parallel, each for comparing potentials of an analog input signal and a reference signal. The controller generates a control signal for controlling the resolution of the analog-to-digital converter. Specifically, the controller controls the number of comparators (CMP) to operate by means of the control signal, thereby determining the resolution. The interpolation circuit interpolates the output data of the comparators that are disabled depending on the resolution. The controller avoids simultaneous operation of two adjoining comparators when the analog-to-digital converter is operated at a resolution lower than its maximum resolution.
摘要翻译： 具有可变分辨率并且允许降低功耗的模数转换装置。 该装置包括并行类型的模数转换器（ADC），控制器和内插电路。 模数转换器具有并联连接的多个比较器，每个比较器用于比较模拟输入信号和基准信号的电位。 控制器产生用于控制模数转换器的分辨率的控制信号。 具体地，控制器通过控制信号控制比较器（CMP）的数量来操作，从而确定分辨率。 内插电路根据分辨率插值禁用的比较器的输出数据。 当模数转换器以低于其最大分辨率的分辨率操作时，控制器避免同时操作两个相邻的比较器。
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公开(公告)号：US20060017827A1
公开(公告)日：2006-01-26
申请号：US11186917
申请日：2005-07-22
申请人： Kuniyuki Tani , Atsushi Wada
发明人： Kuniyuki Tani , Atsushi Wada
IPC分类号： H04N5/20
CPC分类号： H04N5/148 , H03F3/005 , H03F3/45475 , H03F2203/45134 , H03F2203/45138 , H03F2203/45514 , H03F2203/45551 , H03G1/0094 , H04N5/217
摘要： An amplifier circuit is formed by a four-stage variable gain amplifier (VGA) composed of first to fourth VGAs. The variable gain width of each of the four stages of VGAs is 1 to 2. As a whole, the minimum gain is set to 1 whereas the maximum gain is set to 16. The maximum gain of each VGA is small, so that the high-speed operation together with small bias current can be realized.
摘要翻译： 放大器电路由由第一至第四VGA组成的四级可变增益放大器（VGA）形成。 VGA的四级可变增益宽度为1〜2。总体而言，最小增益设为1，而最大增益设定为16.每个VGA的最大增益较小，因此高 可以实现与小偏置电流的速度操作。
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公开(公告)号：US20060012506A1
公开(公告)日：2006-01-19
申请号：US11206907
申请日：2005-08-19
申请人： Atsushi Wada , Shigeto Kobayashi , Kuniyuki Tani
发明人： Atsushi Wada , Shigeto Kobayashi , Kuniyuki Tani
IPC分类号： H03M1/12
摘要： An AD converter capable of achieving both an improved processing speed and a reduced circuit area in good balance. The AD converter pipelines analog-to-digital conversion by using a two-stage configuration consisting of a first conversion unit, or the prior stage, and a second conversion unit, or the subsequent stage. The first conversion unit is a conversion unit of noncyclic type. The second conversion unit is a conversion unit of cyclic type. The second conversion unit is given a conversion processing speed higher than that of the first conversion unit so that the second conversion unit performs cyclic processing twice while the first conversion unit performs conversion processing once.
摘要翻译： AD转换器能够以良好的平衡实现提高的处理速度和减小的电路面积。 AD转换器通过使用由第一转换单元或前一级以及第二转换单元或后续级组成的两级配置来管线模数转换。 第一转换单元是非循环型转换单元。 第二转换单元是循环型转换单元。 给予第二转换单元的转换处理速度高于第一转换单元的转换处理速度，使得第二转换单元在第一转换单元执行转换处理一次的同时进行两次循环处理。
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88.发明申请Complex band-pass delta sigma AD modulator for use in AD converter circuit 失效用于AD转换器电路的复合带通三角ΣAD调制器公开(公告)号：US20050285766A1
公开(公告)日：2005-12-29
申请号：US11157848
申请日：2005-06-22
申请人： Hao San , Haruo Kobayashi , Hiroki Wada , Atsushi Wada
发明人： Hao San , Haruo Kobayashi , Hiroki Wada , Atsushi Wada
CPC分类号： H03M3/34 , H03M1/0665 , H03M3/40 , H03M3/424 , H03M3/464
摘要： A complex band-pass ΔΣ AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.
摘要翻译： 复数带通DeltaSigma AD调制器具有减法器件，复带通滤波器，第一和第二AD转换器以及第一和第二DA转换器。 第一和第二DA转换器和第一和第二逻辑电路夹在第一和第二多路复用器之间。 在时钟信号的第一定时，第一多路复用器原样输入并输出第一和第二数字信号，并且在其第二定时，第一多路复用器输入第一和第二数字信号，并将第一数字信号作为 第二数字信号并输出第二数字信号作为第一数字信号。 第二多路复用器类似地输入和输出第一和第二模拟信号。 通过使用高通和低通元素旋转方法实现复杂的数字和模拟滤波器，第一和第二逻辑电路基本上噪声地形成第一和第二DA转换器的非线性。
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公开(公告)号：US06977604B2
公开(公告)日：2005-12-20
申请号：US10950569
申请日：2004-09-28
申请人： Atsushi Wada , Shigeto Kobayashi , Kuniyuki Tani
发明人： Atsushi Wada , Shigeto Kobayashi , Kuniyuki Tani
摘要： An AD converter capable of achieving both an improved processing speed and a reduced circuit area in good balance. The AD converter pipelines analog-to-digital conversion by using a two-stage configuration consisting of a first conversion unit, or the prior stage, and a second conversion unit, or the subsequent stage. The first conversion unit is a conversion unit of noncyclic type. The second conversion unit is a conversion unit of cyclic type. The second conversion unit is given a conversion processing speed higher than that of the first conversion unit so that the second conversion unit performs cyclic processing twice while the first conversion unit performs conversion processing once.
摘要翻译： AD转换器能够以良好的平衡实现提高的处理速度和减小的电路面积。 AD转换器通过使用由第一转换单元或前一级以及第二转换单元或后续级组成的两级配置来管线模数转换。 第一转换单元是非循环型转换单元。 第二转换单元是循环型转换单元。 给予第二转换单元的转换处理速度高于第一转换单元的转换处理速度，使得第二转换单元在第一转换单元执行转换处理一次的同时进行两次循环处理。
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公开(公告)号：US20050246202A1
公开(公告)日：2005-11-03
申请号：US10451621
申请日：2001-12-25
申请人： Hiroshi Hyoudou , Atsushi Wada
发明人： Hiroshi Hyoudou , Atsushi Wada
摘要： When a medical institution outsources an examination to an external examination institution, a transport identification number generated by a number generating section (16) of the medical institution's data management system (1) is printed out on a barcode label and affixed to a specimen container. The transport identification number is sent along with examination instruction information to a database server (3), and based on the transport identification number read from the barcode label affixed to the specimen container sent by the medical institution, a data management system (2) of the external examination institution obtains examination instruction information from the database server (3) and examinations are performed. The examination results are stored on the database server (3) along with the transport identification number. Based on the transport identification number, the data management system (1) of the medical institution obtains the examination results from the database server (3).
摘要翻译： 当医疗机构将检查外包给外部检查机构时，将由医疗机构的数据管理系统（1）的数字生成部（16）生成的运输识别号码打印在条形码标签上并贴附在检体容器上。 将运输识别号与检查指示信息一起发送到数据库服务器（3），并且基于从由医疗机构发送的标本容器附着的条形码标签读取的运输标识号，将数据管理系统（2） 外部检查机构从数据库服务器（3）获取检查指示信息，并进行检查。 检查结果与运输标识号一起存储在数据库服务器（3）上。 根据运输识别号码，医疗机构的数据管理系统（1）从数据库服务器（3）获取检查结果。
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