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124 条记录 (耗时 0.034 秒)

    Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit
    81.
    发明授权
    Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit 有权
    电源电压降压电路，延迟电路和具有延迟电路的半导体器件

    公开(公告)号：US07456681B2

    公开(公告)日：2008-11-25

    申请号：US11360522

    申请日：2006-02-24

    申请人： Atsunori Hirobe ,  Toru Ishikawa

    发明人： Atsunori Hirobe ,  Toru Ishikawa

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： G05F1/56 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/0013

    摘要： A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset voltage and a manufacturing variation dependent voltage, and an m-time voltage generating circuit. A semiconductor device includes the delay circuit.

    摘要翻译： 延迟电路具有由NMOS或PMOS晶体管主导的电路结构。 延迟电路具有作为电源电压的电源电压降压电路的输出电压，该电源电压降压电路具有用于产生通过偏移电压和制造变化相关电压获得的参考电压的电平发生电路，并且m 时间电压发生电路。 半导体器件包括延迟电路。

    DLL circuit
    82.
    发明申请
    DLL circuit 审中-公开
    DLL电路

    公开(公告)号：US20080094115A1

    公开(公告)日：2008-04-24

    申请号：US11907159

    申请日：2007-10-10

    申请人： Toru Ishikawa

    发明人： Toru Ishikawa

    IPC分类号： H03L7/087 ,  H03L7/08

    CPC分类号： H03L7/0814 ,  H03L7/087

    摘要： A DLL circuit has a rise delay adjustment circuit and a fall delay adjustment circuit. The fall delay adjustment circuit is supplied with a clock adjusted on a rise side in the rise delay adjustment circuit. Since the clock supplied to the fall delay adjustment circuit has already been adjusted on the rise side, a delay difference on a fall side is very small. Therefore, the fall delay adjustment circuit and a fall counter can be drastically reduced in circuit scale. As a consequence, it is possible to obtain the DLL circuit having a small circuit scale and high accuracy.

    摘要翻译： DLL电路具有上升延迟调整电路和下降延迟调整电路。 在上升延迟调整电路中，向下降延迟调整电路提供在上升沿调节的时钟。 由于提供给下降延迟调整电路的时钟已经在上升侧被调整，所以在下降侧的延迟差非常小。 因此，电路规模可以大大降低坠落延迟调整电路和坠落计数器。 结果，可以获得电路规模小，精度高的DLL电路。

    SEMICONDUCTOR MEMORY DEVICE
    83.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20080013392A1

    公开(公告)日：2008-01-17

    申请号：US11773152

    申请日：2007-07-03

    申请人： Toru Ishikawa

    发明人： Toru Ishikawa

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C2211/4061

    摘要： An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the counter outputs coincide with the contents of the storage units; a holding circuit for setting an output hit signal to an active state when a coincidence signal is output from the comparator circuits and for resetting the hit signal to an inactive state in the next following clock cycle; a circuit performing control for not propagating a refresh clock signal to the counter when the hit signal is in an active state and for propagating the refresh clock signal to the counter when the hit signal is in an inactive state; a circuit for replacing an output of the counter by a row address which changes part of the counter output when the hit signal is in an activate state to replace the counter output with the row address whose refresh period is subject to change to output the row address whose refresh period is subject to change as a refresh address.

    摘要翻译： 一种计数器装置，用于存储由刷新周期变化的行地址中断的计数值的存储单元; 比较电路，用于将计数器输出和存储单元的内容彼此比较，以便计数器输出是否与存储单元的内容一致; 保持电路，用于当从比较器电路输出一致信号时将输出命中信号设置为有效状态，并在下一个后续时钟周期将命中信号复位为无效状态; 执行控制，用于当所述命中信号处于活动状态时不向所述计数器传播刷新时钟信号，并且当所述命中信号处于非活动状态时将所述刷新时钟信号传播到所述计数器; 一个电路，用于当命中信号处于激活状态时改变计数器输出的一部分的行地址替换计数器的输出，以用刷新周期改变的行地址替换计数器输出以输出行地址 刷新周期可能会随刷新地址而变化。

    Data transmission system and data transmission apparatus
    84.
    发明申请
    Data transmission system and data transmission apparatus 失效

    公开(公告)号：US20070300097A1

    公开(公告)日：2007-12-27

    申请号：US11890438

    申请日：2007-08-06

    申请人： Toru Ishikawa

    发明人： Toru Ishikawa

    IPC分类号： G06F1/12

    CPC分类号： G06F13/423 ,  H04L7/0008

    摘要： A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of a slave side clock signal (CLKSOUT), output sections (33-1 to 33-m) for outputting transmission data signals (SD1 to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section (34) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT). Master device (10) may include a master side clock signal generator section (11) for generating master side clock signal (CLKM), input sections (12-1 to 12-m) for sampling data signals (SD1 to SDm) in response to master side clock signal (CLKM), and a phase compare circuit (19) for generating a phase adjustment instruction signal (SADJOUT) based upon timing reference signal (SSPH) and master side clock signal (CLKM). Phase adjusting circuit (40) may adjust a phase of slave side clock signal (CLKSOUT) in response to phase adjustment instruction signal (SADJOUT). In this way, data setup and/or hold times may be improved.

    Fuel injector
    86.
    发明授权
    Fuel injector 失效
    喷油器

    公开(公告)号：US06845925B2

    公开(公告)日：2005-01-25

    申请号：US09989068

    申请日：2001-11-21

    申请人： Motoyuki Abe ,  Yoshio Okamoto ,  Yuzo Kadomukai ,  Makoto Yamakado ,  Ayumu Miyajima ,  Toru Ishikawa ,  Yasuo Namaizawa

    发明人： Motoyuki Abe ,  Yoshio Okamoto ,  Yuzo Kadomukai ,  Makoto Yamakado ,  Ayumu Miyajima ,  Toru Ishikawa ,  Yasuo Namaizawa

    IPC分类号： F02M51/06 ,  F02M61/16 ,  F02M61/18 ,  F02M61/00

    CPC分类号： F02M61/1806 ,  F02M51/061 ,  F02M61/162

    摘要： To produce a fuel spray that is asymmetrical in the flow rate distribution of a sprayed fuel in order to improve the homogeneity of air-fuel mixture density during the air intake stroke injection for homogeneous combustion in an in-cylinder injection engine, the exit portion of the fuel injection hole is provided with the wall surfaces 204a, 204b, 205a, and 205b that are parallel to the central axis of the injection hole. Also, the periphery of the injection hole is provided with a plurality of areas in which the flow of the fuel in the radial direction of the injection hole will be restrained, and an plurality of areas in which the flow of the fuel in the radial direction of the injection hole will not be restrained, and a different size is assigned to each non-restraint area.

    摘要翻译： 为了在喷射燃料的流量分布中产生不对称的燃料喷雾，以便在缸内喷射发动机的均匀燃烧的进气冲程喷射期间提高空气 - 燃料混合物密度的均匀性， 燃料喷射孔设置有与喷射孔的中心轴线平行的壁面204a，204b，205a，205b。 此外，喷射孔的周边设置有多个区域，其中燃料在喷射孔的径向方向上的流动将被抑制，并且燃料在径向上的流动的多个区域 不会限制注入孔，并且对每个非约束区域分配不同的尺寸。

    Sense amplifier arrangement for semiconductor memory device
    87.
    发明授权
    Sense amplifier arrangement for semiconductor memory device 有权
    用于半导体存储器件的感测放大器装置

    公开(公告)号：US06678194B2

    公开(公告)日：2004-01-13

    申请号：US10053742

    申请日：2002-01-22

    申请人： Toru Ishikawa

    发明人： Toru Ishikawa

    IPC分类号： G11C700

    CPC分类号： G11C7/18 ,  G11C11/4097 ,  H01L27/10897

    摘要： A semiconductor memory device including a plurality of cell arrays (121 to 128) and a plurality of sense amplifier sections is disclosed. Adjacent cell arrays may have a sense amplifier section disposed between. Sense amplifiers (131 to 163) within a sense amplifier section may be connected to a bit line that is connected to a plurality of memory cells in more than one of the cell arrays (121 to 128). When a cell array (123) is activated, sense amplifier sections that may be distributed around edges of a plurality of cell arrays (122 to 124) may be activated to sense data from the activated cell array (123). In this way, current may be distributed and noise may be reduced. An activated bit line (227) may be adjacent to a precharged bit line (250) in a non-activated cell array (124). In this way, cross-talk between activated bit lines may be reduced.

    摘要翻译： 公开了一种包括多个单元阵列（121至128）和多个读出放大器部分的半导体存储器件。 相邻的单元阵列可以具有设置在其间的读出放大器部分。 感测放大器部分内的感测放大器（131至163）可以连接到连接到多个单元阵列（121至128）中的多个存储器单元的位线。 当激活单元阵列（123）时，可以激活可以分布在多个单元阵列（122至124）的边缘周围的感测放大器部分，以感测来自激活的单元阵列（123）的数据。 以这种方式，电流可能被分配并且可能降低噪声。 激活的位线（227）可以与未激活的单元阵列（124）中的预充电位线（250）相邻。 以这种方式，可以减少激活的位线之间的串扰。

    DLL circuit, semiconductor device using the same and delay control method
    88.
    发明授权
    DLL circuit, semiconductor device using the same and delay control method 有权
    DLL电路，使用相同的半导体器件和延迟控制方法

    公开(公告)号：US06509776B2

    公开(公告)日：2003-01-21

    申请号：US09828002

    申请日：2001-04-06

    申请人： Shotaro Kobayashi ,  Toru Ishikawa

    发明人： Shotaro Kobayashi ,  Toru Ishikawa

    IPC分类号： H03H1126

    CPC分类号： H03L7/091 ,  H03K5/133 ,  H03L7/0812 ,  Y10S331/02

    摘要： A DLL (delay locked loop) circuit includes a signal propagation system and a delay control system. The signal propagation system includes a delay circuit which delays a reference clock signal based on a delay control signal to generate a delayed clock signal. The delay control system includes a sampling circuit, a phase comparing circuit and a delay control circuit. The sampling circuit outputs a first clock signal having a pulse corresponding to one of n (n is an integer more than 1) pulses of the delayed clock signal. The phase comparing circuit compares the first clock signal as a first comparison input signal and the reference clock signal as a second comparison input signal in phase to output a phase difference. The delay control circuit generates the delay control signal based on the phase difference from the phase comparing circuit to output to the delay circuit of the signal propagation system.

    摘要翻译： DLL（延迟锁定环路）电路包括信号传播系统和延迟控制系统。 信号传播系统包括延迟电路，其基于延迟控制信号延迟参考时钟信号以产生延迟的时钟信号。 延迟控制系统包括采样电路，相位比较电路和延迟控制电路。 采样电路输出具有对应于延迟的时钟信号的n（n是大于1的整数）脉冲之一的脉冲的第一时钟信号。 相位比较电路将作为第一比较输入信号的第一时钟信号和参考时钟信号作为相位的第二比较输入信号进行比较，以输出相位差。 延迟控制电路基于与相位比较电路的相位差产生延迟控制信号，输出到信号传播系统的延迟电路。

    Semiconductor memory device capable of storing high potential level of data
    89.
    发明授权
    Semiconductor memory device capable of storing high potential level of data 失效
    能够存储高电位数据的半导体存储器件

    公开(公告)号：US5719814A

    公开(公告)日：1998-02-17

    申请号：US719880

    申请日：1996-09-25

    申请人： Toru Ishikawa

    发明人： Toru Ishikawa

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C8/08 ,  G11C11/407 ,  G11C11/4091 ,  G11C7/00

    CPC分类号： G11C8/08 ,  G11C11/4091 ,  G11C7/065

    摘要： In a semiconductor memory device, a row decoder is connected to a plurality of word lines to select one of the plurality of word lines in response to a row address. A word line driving section drives, in response to a row address strobe signal, the selected word line to a first potential higher by a predetermined potential than a predetermined second potential, for a read or write operation to a selected memory cell connected to the selected word line and a selected pair of bit lines. The second potential is higher than a power supply higher side potential. A sense amplifier activating section issues sense amplifier activating signals for the write operation to the selected memory cell in response to a sense control signal such that a data having a potential higher than the power supply higher side potential can be written or rewritten in the selected memory cell. Each of a plurality of sense amplifiers amplifies the data on corresponding pair of bit lines in response to the sense amplifier activating signals. In the read operation, the read data is outputted from an input/output section via a column selecting section for selecting and connecting one of the plurality of pairs of bit lines to the input/output section in response to a column address.

    摘要翻译： 在半导体存储器件中，行解码器被连接到多个字线以响应于行地址来选择多个字线之一。 字线驱动部分响应于行地址选通信号将所选择的字线驱动到比预定的第二电位高预定电位的第一电位，以便对连接到所选择的所选择的存储单元进行读或写操作 字线和一对选定的位线。 第二个电位高于电源较高侧电位。 感测放大器激活部分响应于感测控制信号，向感应放大器激活信号以对所选择的存储器单元进行写操作，使得具有高于电源较高侧电位的电位的数据可被写入或改写在所选择的存储器中 细胞。 多个读出放大器中的每一个响应于读出放大器激活信号而放大对应的位线对上的数据。 在读取操作中，读取数据经由列选择部分从输入/输出部分输出，用于响应于列地址选择并连接多对位线之一到输入/输出部分。