公开(公告)号：US11950415B2

公开(公告)日：2024-04-02

申请号：US17162524

申请日：2021-01-29

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240071502A1

公开(公告)日：2024-02-29

申请号：US17822712

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

IPC: G11C16/08 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: G11C16/08 ,  H01L21/76843 ,  H01L21/76831 ,  H01L21/76885 ,  H01L27/1157 ,  H01L27/11578

Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).

公开(公告)号：US11895835B2

公开(公告)日：2024-02-06

申请号：US17348021

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: H10B43/27 ,  H10B41/27 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  G11C5/02

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H01L23/5384 ,  H10B43/27

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an tipper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the tipper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): a hafnium oxide; (b): a bilayer comprising silicon nitride and comprising silicon dioxide positioned vertically relative one another, the silicon nitride in the bilayer being closer to the intervening-material layer than is the silicon dioxide in the bilayer; and (c): SiOxNy, where each of “x” and “y” is from 1 atomic percent to 90 atomic percent of the total of the Si, the O, and the N in the SiOxNy. Methods are disclosed.

公开(公告)号：US11721629B2

公开(公告)日：2023-08-08

申请号：US17381991

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：US20230209810A1

公开(公告)日：2023-06-29

申请号：US18046088

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/7682 ,  H01L27/1087 ,  H01L21/76837

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus. A computing system includes the memory device.

公开(公告)号：US20230207011A1

公开(公告)日：2023-06-29

申请号：US17583651

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through the insulative tiers and the conductive tiers into the conductor tier. Individual of the TAVs comprises an upper portion directly above and joined with a lower portion. The individual TAVs in a vertical cross-section comprises at least one external upper jog surface. The individual TAVs comprise at least one external lower jog surface in the conductor tier in the vertical cross-section and that is below the upper jog surface. Other embodiments, including method, are disclosed.

公开(公告)号：US20230171960A1

公开(公告)日：2023-06-01

申请号：US18096264

申请日：2023-01-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

公开(公告)号：US20230062403A1

公开(公告)日：2023-03-02

申请号：US17508143

申请日：2021-10-22

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Chet E. Carter ,  Justin D. Shepherdson ,  Collin Howder ,  Joshua Wolanyk

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US11581330B2

公开(公告)日：2023-02-14

申请号：US17091668

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11565

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Dummy pillars extend through the insulative tiers and the conductive tiers. A lowest of the conductive tiers comprises conducting material and dummy-region material that is aside and of different composition from that of the conducting material. The channel-material strings extend through the conducting material of the lowest conductive tier. The dummy pillars extend through the dummy-region material of the lowest conductive tier. Other embodiments, including method, are disclosed.

公开(公告)号：US20230039517A1

公开(公告)日：2023-02-09

申请号：US17396056

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Purnima Narayanan ,  Vinayak Shamanna ,  Justin D. Shepherdson

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.