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    VERTICAL MEMORY ARCHITECTURE
    83.
    发明公开
    VERTICAL MEMORY ARCHITECTURE 审中-公开

    公开(公告)号：US20230262995A1

    公开(公告)日：2023-08-17

    申请号：US17651217

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1683

    Abstract: Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

    Polarity-written cell architectures for a memory device
    85.
    发明授权
    Polarity-written cell architectures for a memory device 有权

    公开(公告)号：US11721394B2

    公开(公告)日：2023-08-08

    申请号：US17511484

    申请日：2021-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/005 ,  G11C2013/0073

    Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.

    DECODING ARCHITECTURE FOR MEMORY DEVICES
    86.
    发明公开
    DECODING ARCHITECTURE FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20230238050A1

    公开(公告)日：2023-07-27

    申请号：US18100802

    申请日：2023-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Enrico Varesi ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C11/408 ,  G11C5/06 ,  G11C11/4074

    CPC classification number: G11C11/4085 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4087

    Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Two word line plates in a same plane may be activated via a shared electrode. Memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

    Two memory cells sensed to determine one data value
    87.
    发明授权
    Two memory cells sensed to determine one data value 有权

    公开(公告)号：US11670367B2

    公开(公告)日：2023-06-06

    申请号：US17486134

    申请日：2021-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2013/0057 ,  G11C2213/15

    Abstract: Apparatuses, methods, and systems for sensing two memory cells to determine one data value are described herein. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two memory cells to determine one data value. One data value is determined by sensing the memory state of a first one of the two memory cells using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing the memory state of a second one of the two memory cells using a second sensing voltage in the sense window. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.

    Identify the programming mode of memory cells during reading of the memory cells
    88.
    发明授权
    Identify the programming mode of memory cells during reading of the memory cells 有权

    公开(公告)号：US11615854B2

    公开(公告)日：2023-03-28

    申请号：US17221420

    申请日：2021-04-02

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

    IPC: G11C7/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

    Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

    SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES
    89.
    发明申请
    SELF-SELECTING MEMORY ARRAY WITH HORIZONTAL ACCESS LINES 有权

    公开(公告)号：US20230005535A1

    公开(公告)日：2023-01-05

    申请号：US17864015

    申请日：2022-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Lorenzo Fratin ,  Fabio Pellizzer ,  Agostino Pirovano ,  Russell L. Meyer

    IPC: G11C13/00 ,  H01L23/528

    Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

    Memory array with graded memory stack resistances
    90.
    发明授权
    Memory array with graded memory stack resistances 有权

    公开(公告)号：US11538860B2

    公开(公告)日：2022-12-27

    申请号：US17130215

    申请日：2020-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Lorenzo Fratin ,  Hongmei Wang

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L21/66 ,  H01L23/532

    Abstract: Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

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