公开(公告)号：US09779819B1

公开(公告)日：2017-10-03

申请号：US15191786

申请日：2016-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459

Abstract: In an example, a programming method includes applying a program voltage to a selected access line commonly connected to a first memory cell of a first string of series-connected memory cells and to a second memory cell of a second string of series-connected memory cells while a data line is electrically connected to the first memory cell and electrically disconnected from the second memory cell, and while continuing to apply the program voltage to the selected access line, electrically disconnecting the data line from the first memory cell and subsequently electrically connecting the data line to the second memory cell.

公开(公告)号：US09620234B2

公开(公告)日：2017-04-11

申请号：US15233097

申请日：2016-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ramin Ghodsi

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/10 ,  G06F11/1008 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/349

Abstract: Methods for reading data that was functionally stored include reading a pattern of threshold voltages from a particular group of memory cells, determining which pattern, of a plurality of patterns, matches the read pattern, and determining a group of decoded data associated with the pattern determined to match the read pattern.

公开(公告)号：US09595339B2

公开(公告)日：2017-03-14

申请号：US14518727

申请日：2014-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

Abstract translation: 本文描述了用于减少读取干扰的装置和方法。 示例性装置可以包括包括第一选择栅极漏极（SGD）开关和第一选择栅极源（SGS）开关的第一存储器子块，包括第二SGD开关和第二SGS开关的第二存储器子块以及与之相关联的存取线 与第一和第二存储器子块。 该装置可以包括控制单元，其被配置为在读取操作的第一部分期间使第一和第二SGD开关以及第一和第二SGS开关能够实现，并且在第一部分期间在存取线上提供第一电压。 控制单元可以被配置为在读操作的第二部分期间禁用第一SGD开关和第一SGS开关，并且在第二部分期间在接入线上提供第二电压。

公开(公告)号：US09525341B2

公开(公告)日：2016-12-20

申请号：US14581710

申请日：2014-12-23

Applicant: Micron Technology, Inc.

Inventor： Feng Pan ,  Ramin Ghodsi

IPC: H02M3/156 ,  G05F1/59

CPC classification number: H02M3/156 ,  G05F1/59

Abstract: Some embodiments include apparatuses having a switch regulator that includes a first circuit with a first comparator to compare an output of the switch regulator to a first reference voltage, and to provide a control signal to enable or disable a first pass element based on the comparison. The switch regulator includes at least a second circuit having a second comparator to compare an output of the switch regulator to a second reference voltage that is lower than the first reference voltage, and to provide a control signal to enable or disable a second pass element based on the comparison. The switch regulator does not include Miller compensation circuits. Other apparatuses and methods according to other embodiments are described.

Abstract translation: 一些实施例包括具有开关调节器的装置，该开关调节器包括具有第一比较器的第一电路，用于将开关调节器的输出与第一参考电压进行比较，并且基于该比较来提供控制信号以启用或禁用第一通过元件。 开关调节器至少包括具有第二比较器的第二电路，用于将开关调节器的输出与低于第一参考电压的第二参考电压进行比较，并且提供控制信号以使第二通过元件基于 比较。 开关稳压器不包括米勒补偿电路。 描述根据其他实施例的其他装置和方法。

公开(公告)号：US20160351265A1

公开(公告)日：2016-12-01

申请号：US15233097

申请日：2016-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ramin Ghodsi

IPC: G11C16/26 ,  G11C16/10

CPC classification number: G11C16/10 ,  G06F11/1008 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/349

Abstract: Methods for reading data that was functionally stored include reading a pattern of threshold voltages from a particular group of memory cells, determining which pattern, of a plurality of patterns, matches the read pattern, and determining a group of decoded data associated with the pattern determined to match the read pattern.

Abstract translation: 用于读取功能存储的数据的方法包括从特定存储单元组读取阈值电压的模式，确定多个模式中的哪个模式与读取模式匹配，以及确定与所确定的模式相关联的解码数据组 以匹配读取模式。

公开(公告)号：US20160225420A1

公开(公告)日：2016-08-04

申请号：US15095347

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Qiang Tang ,  Ramin Ghodsi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

Abstract translation: 公开了用于存储器输入定时自校准的方法，用于输入定时自校准的装置和系统。 一种这样的方法包括将多个延迟微调设置顺序地编程到数据路径的延迟电路中。 数据路径可以包括耦合到延迟电路的数据锁存器。 时钟耦合到数据锁存器，将数据时钟数据插入数据锁存器。 数据的转换基本上与时钟的转换对齐。 在对每个延迟微调设置进行编程后，读取数据锁存器的输出。 在数据锁存器的第一输出状态和数据锁存器的第二输出状态之间确定边界，其中边界与多个延迟调整设置的特定延迟微调设置相关联。 特定的延迟调整设置被编程到延迟电路中。

公开(公告)号：US20160163388A1

公开(公告)日：2016-06-09

申请号：US14558900

申请日：2014-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Ramin Ghodsi

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

Abstract: An embodiment of a method of programing might include applying a first voltage difference across a first memory cell to be programed, where applying the first voltage difference comprises applying a first channel bias voltage to a channel of the first memory cell, and applying a second voltage difference, substantially equal to the first voltage difference, across a second memory cell to be programed while applying the first voltage difference across the first memory-cell, where applying the second voltage difference comprises applying a second channel bias voltage to a channel of the second memory cell. The first channel bias voltage is different than the second channel bias voltage, and the first memory cell and the second memory cell are commonly coupled to an access line and are at different locations along a length of the access line.

Abstract translation: 编程方法的一个实施例可以包括在要编程的第一存储器单元上施加第一电压差，其中施加第一电压差包括将第一通道偏置电压施加到第一存储器单元的通道，以及施加第二电压 在施加第一电压差的同时在第一存储单元施加第一电压差的情况下跨越待编程的第二存储器单元的基本上等于第一电压差的差值，其中施加第二电压差包括将第二通道偏置电压施加到第二电压差的通道 记忆单元 第一通道偏置电压不同于第二通道偏置电压，并且第一存储器单元和第二存储单元通常耦合到接入线，并且沿着接入线的长度在不同的位置。

公开(公告)号：US20150357031A1

公开(公告)日：2015-12-10

申请号：US14299074

申请日：2014-06-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Xiaojiang Guo ,  Ramin Ghodsi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G06F12/02 ,  G06F3/06

CPC classification number: G11C11/5628 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

Abstract: Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level.

Abstract translation: 提供了用于编程具有多步编程脉冲的存储器的存储器和方法。 一种方法包括将多个编程脉冲施加到要编程的存储器件的单元，其中多个编程脉冲的每个编程脉冲被配置为有助于将多个单元的单元编程为多个单元的每个数据状态 编程数据状态。 每个编程脉冲的第一部分用于将某些单元格编程为与第一阈值电压电平相关联的目标数据状态，并且每个编程脉冲的稍后部分用于将其它单元编程为与第二阈值相关联的目标数据状态 电压电平低于第一阈值电压电平。

公开(公告)号：US20150279432A1

公开(公告)日：2015-10-01

申请号：US14735350

申请日：2015-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip ,  Mark A. Helm ,  Ramin Ghodsi

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C11/06035 ,  G11C11/06064 ,  G11C11/063 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/11531 ,  H01L27/11573 ,  Y10T29/49069

Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.

Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。

公开(公告)号：US08971127B2

公开(公告)日：2015-03-03

申请号：US14034266

申请日：2013-09-23

Applicant: Micron Technology, Inc.

Inventor： Ramin Ghodsi ,  Qiang Tang

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/12

Abstract: A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.

Abstract translation: 一种对非易失性存储单元中的浮置栅极进行充电的方法包括：使存储单元内的衬底沟道达到第一电压，使控制栅极达到编程电压，并且在控制栅极处于编程电压的同时浮置衬底沟道电压 。 存储器件包括可操作以执行所述方法的状态机或控制器，并描述了这种状态机，存储器件和信息处理系统的操作。