公开(公告)号：US11380379B2

公开(公告)日：2022-07-05

申请号：US17087085

申请日：2020-11-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: G11C7/24 ,  H04L9/32 ,  G06F21/44

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

公开(公告)号：US10891184B2

公开(公告)日：2021-01-12

申请号：US16419430

申请日：2019-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Yi-Fan Chang

IPC: G06F3/06 ,  G06F11/10

Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

公开(公告)号：US10855477B2

公开(公告)日：2020-12-01

申请号：US15857341

申请日：2017-12-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

IPC: G06F11/30 ,  H04L9/32 ,  H04L9/08 ,  G09C1/00

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US10749695B2

公开(公告)日：2020-08-18

申请号：US16592850

申请日：2019-10-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

IPC: G06F13/00 ,  H04L9/32 ,  G06F3/06 ,  G09C1/00 ,  G11C16/22 ,  H04L9/08 ,  H04L9/14 ,  G11C11/16 ,  G11C13/00 ,  G06F7/58 ,  G06F11/10 ,  G06F12/02 ,  G06F12/14 ,  G06F21/31 ,  G06F21/60 ,  G06F21/75 ,  G11C7/24 ,  G11C16/10 ,  G11C16/26 ,  G11C8/20 ,  G06F13/42 ,  G11C7/10

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

公开(公告)号：US10658046B2

公开(公告)日：2020-05-19

申请号：US15841622

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Chun-Yu Liao

IPC: G11C7/10 ,  G11C16/26 ,  G11C16/04 ,  G11C7/06 ,  G06F12/02 ,  G11C11/4093 ,  G06F13/40 ,  G11C16/20

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

公开(公告)号：US10566062B2

公开(公告)日：2020-02-18

申请号：US15841598

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Shang-Chi Yang

IPC: G11C7/10 ,  G11C16/26 ,  G11C7/06 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F3/06 ,  G11C11/4093 ,  G11C16/22 ,  G11C7/22 ,  G11C16/04 ,  G11C7/24

Abstract: A memory device is disclosed in the present invention, comprising a memory array, a logic circuit, a sense amplifier circuit and a read buffer. The logic circuit is configured to perform a read operation in response to a read command and a start address. During the read operation, the logic circuit finds a target data in the memory array. The sense amplifier circuit is configured to read the target data from the memory array during the read operation. The read buffer is configured to temporarily stores and outputs the target data during the read operation. When an interruption event occurs during the read operation, the read buffer preserves a buffer content of the read buffer, and the logic circuit records a read status.

公开(公告)号：US10162751B2

公开(公告)日：2018-12-25

申请号：US15139252

申请日：2016-04-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

IPC: G06F12/06

Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

公开(公告)号：US09881654B2

公开(公告)日：2018-01-30

申请号：US14877723

申请日：2015-10-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wu-Chin Peng ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun Hsiung Hung

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: An integrated circuit comprises a power supply input pin receiving an off-chip supply voltage having a variable current, an on-chip power source powered by the off-chip supply voltage and providing a regulated current, a memory array, and a set of one or more circuits coupled to the memory array and powered by the regulated current from the on-chip power source. The IC can include control circuitry performing memory operations on the memory array, said control circuitry powered by at least the off-chip supply voltage from the power supply pin.

公开(公告)号：US09876493B2

公开(公告)日：2018-01-23

申请号：US14693565

申请日：2015-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yi-Fan Chang ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C8/00 ,  H03K17/00 ,  G11C8/10

CPC classification number: H03K17/007 ,  G11C8/00 ,  G11C8/10 ,  H03K2217/0036

Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

公开(公告)号：US09628061B2

公开(公告)日：2017-04-18

申请号：US14860761

申请日：2015-09-22

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Ming Lu ,  Chun-Hsiung Hung ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang

IPC: H03K5/153 ,  H03K5/1534

CPC classification number: H03K5/1534

Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.