公开(公告)号：US20110147798A1

公开(公告)日：2011-06-23

申请号：US12646711

申请日：2009-12-23

申请人： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

发明人： Marko Radosavljevic ,  Prashant Majhi ,  Jack T. Kavalieros ,  Niti Goel ,  Wilman Tsai ,  Niloy Mukherjee ,  Yong Ju Lee ,  Gilbert Dewey ,  Willy Rachmady

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

摘要翻译： 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US20180226509A1

公开(公告)日：2018-08-09

申请号：US15747925

申请日：2015-07-31

申请人： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Elijah V. Karpov ,  Prashant Majhi ,  Roza Kotlyar ,  Niloy Mukherjee ,  Charles C. Kuo ,  Uday Shah ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L29/786 ,  H01L27/07 ,  H01L27/12 ,  H01L29/49 ,  H01L29/02

CPC分类号： H01L29/7869 ,  H01L27/0705 ,  H01L27/1225 ,  H01L27/2436 ,  H01L29/02 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78642 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

公开(公告)号：US10516109B2

公开(公告)日：2019-12-24

申请号：US15529907

申请日：2014-12-24

申请人： Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Ravi Pillarisetty ,  Prashant Majhi ,  Uday Shah ,  Ryan E Arch ,  Markus Kuhn ,  Justin S. Brockman ,  Huiying Liu ,  Elijah V Karpov ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L45/00

摘要： Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

公开(公告)号：US10355205B2

公开(公告)日：2019-07-16

申请号：US15528674

申请日：2014-12-18

申请人： Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Uday Shah ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

发明人： Prashant Majhi ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Uday Shah ,  Elijah V. Karpov ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： H01L29/08 ,  H01L45/00

摘要： Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.

公开(公告)号：US09934976B2

公开(公告)日：2018-04-03

申请号：US12317180

申请日：2008-12-18

申请人： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S Chau

发明人： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S Chau

IPC分类号： H01L21/285 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/76814

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

公开(公告)号：US20100327377A1

公开(公告)日：2010-12-30

申请号：US12459254

申请日：2009-06-26

申请人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

发明人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/31 ,  H01L21/3205

CPC分类号： H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

摘要翻译： 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。

公开(公告)号：US20100155954A1

公开(公告)日：2010-06-24

申请号：US12317180

申请日：2008-12-18

申请人： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S. Chau

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/76814

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在设置在基板上的层间电介质（ILD）中形成接触开口，其中暴露源极/漏极接触区域，在源极/漏极接触区域上形成稀土金属层，形成过渡金属层 在稀土金属层上; 并对稀土金属层和过渡金属层退火以形成金属硅化物堆叠结构。

公开(公告)号：US20100052166A1

公开(公告)日：2010-03-04

申请号：US12229881

申请日：2008-08-26

申请人： Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kayalieros ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kayalieros ,  Robert S. Chau

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76867 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of an apparatus and methods for forming enhanced contacts using sandwiched metal structures are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述使用夹层金属结构形成增强触点的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US08952541B2

公开(公告)日：2015-02-10

申请号：US13352062

申请日：2012-01-17

申请人： Niloy Mukherjee ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack Kavalieros ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/768 ,  H01L29/08 ,  H01L23/485 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/285 ,  H01L29/51

CPC分类号： H01L29/517 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/452 ,  H01L29/456 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.

摘要翻译： 接触可以通过包括在具有晶体管的衬底上沉积电介质层的方法来制造，蚀刻延伸到源极区的电介质层中的第一开口，在源区上形成绝缘体，在绝缘体上形成接触金属 所述绝缘体将所述接触金属与所述源极区分离，并且基本上填充所述第一开口，其中所述接触金属在所述第一开口被填充之后保持与所述源极区分离。

公开(公告)号：US08878363B2

公开(公告)日：2014-11-04

申请号：US12459254

申请日：2009-06-26

申请人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

发明人： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/47 ,  H01L23/485 ,  H01L29/78 ,  H01L21/285 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

摘要翻译： 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。