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公开(公告)号：US20240237360A1
公开(公告)日：2024-07-11
申请号：US18617466
申请日：2024-03-26
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto , Ferdinando Bedeschi , Umberto di Vincenzo
CPC classification number: H10B63/84 , G11C13/0004 , G11C13/003 , H10N70/231 , G11C2213/71
Abstract: An array of memory cells in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels.
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公开(公告)号：US20240194272A1
公开(公告)日：2024-06-13
申请号：US18586134
申请日：2024-02-23
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Riccardo Muzzetto , Umberto Di Vincenzo
Abstract: The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.
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公开(公告)号：US20240103741A1
公开(公告)日：2024-03-28
申请号：US17952614
申请日：2022-09-26
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Christophe Vincent Antoine Laurent , Riccardo Muzzetto
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0629 , G06F3/0679
Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.
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公开(公告)号：US11848038B2
公开(公告)日：2023-12-19
申请号：US17986522
申请日：2022-11-14
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto
CPC classification number: G11C11/2297 , G06F13/4022 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C2013/0057
Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.
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公开(公告)号：US20230282301A1
公开(公告)日：2023-09-07
申请号：US18112307
申请日：2023-02-21
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
CPC classification number: G11C29/42 , G11C29/44 , G11C7/14 , G11C29/20 , G11C29/12005
Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
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Patent Agency Ranking
公开(公告)号：US11670368B2
公开(公告)日：2023-06-06
申请号：US17512586
申请日：2021-10-27
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
CPC classification number: G11C13/004 , G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0045
Abstract: A method for reading memory cells is described. The method may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.
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公开(公告)号：US20230110946A1
公开(公告)日：2023-04-13
申请号：US17044150
申请日：2020-05-13
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto , Ferdinando Bedeschi , Umberto di Vincenzo
IPC: G06F3/06
Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.
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公开(公告)号：US20230071819A1
公开(公告)日：2023-03-09
申请号：US17986522
申请日：2022-11-14
Applicant: Micron Technology, Inc.
Inventor： Riccardo Muzzetto
Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.
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公开(公告)号：US11594297B2
公开(公告)日：2023-02-28
申请号：US17590532
申请日：2022-02-01
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Riccardo Muzzetto , Ferdinando Bedeschi
Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
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公开(公告)号：US11587604B2
公开(公告)日：2023-02-21
申请号：US17241889
申请日：2021-04-27
Applicant: Micron Technology, Inc.
Inventor： Umberto Di Vincenzo , Ferdinando Bedeschi , Riccardo Muzzetto
IPC: G11C11/22
Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.
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